초록 ▼

A ratio-logic system having an input sensing device and a resetable delay device is disclosed. The input sensing device receives an input having a first logic state and a second input having a second logic state. The input sensing device then asynchronously outputs a first state-change signal if the

A ratio-logic system having an input sensing device and a resetable delay device is disclosed. The input sensing device receives an input having a first logic state and a second input having a second logic state. The input sensing device then asynchronously outputs a first state-change signal if the first logic state differs from the logic state of a previous input, and a second state-change signal if the second logic state differs from the first logic state. The resetable delay device receives the first and second state-change signals and asynchronously outputs a power-up signal to a ratio-logic device for a predetermined amount of time after the first state-change signal is received. The resetable delay device then powers-down the ratio-logic device after the predetermined amount of time is over. The predetermined amount of time is reset if the input sensing device receives the second state-change signal before the predetermined amount of time is over.

대표청구항 ▼

[ What is claimed is:] [1.] A circuit for a ratio-logic device comprising:an input sensing device for receiving a first input having a first state and a second input having a second state, asynchronously outputting a first state-change signal if said first state differs from a state of a previous in

[ What is claimed is:] [1.] A circuit for a ratio-logic device comprising:an input sensing device for receiving a first input having a first state and a second input having a second state, asynchronously outputting a first state-change signal if said first state differs from a state of a previous input and asynchronously outputting a second state-change signal if said second state differs from said first state; anda resetable delay device, coupled to said input sensing device and the ratio-logic device, for receiving said first and second state-change signal and asynchronously outputting a power-up signal to said ratio-logic device for a predetermined amount of time after said first state-change signal is received, and outputting a power-down signal to said ratio-logic device after said predetermined amount of time is over,wherein said predetermined amount of time is reset if said resetable delay device receives said second state-change signal before said predetermined amount of time is over.