[특허]In-situ etch of BARC layer during formation of local interconnects

[미국특허] In-situ etch of BARC layer during formation of local interconnects 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/306
출원번호	US-0924572 (1997-09-05)
발명자 / 주소	Wang Fei Holbrook Allison Kai James K.
출원인 / 주소	Advanced Micro Devices, Inc.
인용정보	피인용 횟수 : 35 인용 특허 : 15

초록 ▼

An in-situ etching process for creating local interconnects in a semiconductor device includes using one etching tool to: etch through an organic, or inorganic BARC layer using O.sub.2 gas, or C.sub.2 F.sub.6 /O.sub.2 gases, respectively; a masked dielectric layer to a stop layer using a mixture of C.sub.4 F.sub.8, CH.sub.3 F and argon (Ar) gasses; etch away the mask layer using a mixture of O.sub.2 and Ar gasses; and, etch through the stop layer using a mixture of CH.sub.3 F gas and O.sub.2 gas. Remaining portions of the BARC layer, whether organic or inorganic, are also removed during the in-situ etching process using appropriate gases. The method then includes depositing conductive material within the openings that were etched to form local interconnects.

대표청구항 ▼

[ What is claimed is:] [1.] A method for forming openings in a semiconductor wafer having a plurality of layers including a bottom anti-reflective layer, the method comprising:using a single etching tool to etch through selected portions of a bottom anti-reflective layer, wherein the selected portions of the bottom anti-reflective layer are defined by etch windows formed by a mask layer above the bottom anti-reflective layer;using the etching tool to etch through selected portions of a first underlying layer below the bottom anti-reflective layer, wherein the selected portions of the first underlying layer are defined by extended etch windows formed by the bottom anti-reflective layer above the first underlying layer;using the etching tool to substantially etch away the mask layer using O.sub.2 gas;using the etching tool to etch through selected portions of a second underlying layer that is below the first underlying layer using a mixture of CH.sub.3 F gas and O.sub.2 gas, wherein the selected portions of the second underlying layer are defined by etched openings in the first underlying layer corresponding to the extended etch windows.

이 특허에 인용된 특허 (15)

Chan Tsiu C. (Carollton TX) Bryant Frank R. (Denton TX) Walters John L. (Carrollton TX), Local interconnect structure.
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Rahman M. Dalil (Warwick RI), Metal ion reduction in bottom anti-reflective coatings for use in semiconductor device formation.
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Abernathey John R. (Underhill VT) Mann Randy W. (Jericho VT) Parries Paul C. (Essex Junction VT) Springer Julie A. (Burlington VT), Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits.
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Blanchard Richard A. (Los Altos CA), Method for forming a semiconductor structure with self-aligned contacts.
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Chen Fusen (Dallas TX) Liou Fu-Tai (Carrollton TX) Dixit Girish (Dallas TX), Method for forming local interconnect for integrated circuits.
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Jeng Erik S.,TWX ; Yen Tzu-Shih,TWX, Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits.
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Wilmsmeyer Klaus (Denzlingen DEX), Method of fabricating semiconductor devices in CMOS technology with local interconnects.
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Chin Daeje (Seoul NY KRX) Dhong Sang H. (Mahopac NY), Method of making ultra dense dram cells.
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Kim Paul S. (Wappingers Falls NY) Ogura Seiki (Hopewell Junction NY), Method of manufacturing local interconnection for semiconductors.
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Lee Jin-Yuan,TWX ; Liang Mong-Song,TWX, Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide,.
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Okabe Kazuhiro (Tokyo JPX), Process for fabricating complementary field effect transistors having a direct contact electrode.
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Nasr Andre I. (Marlboro MA), Semiconductor device fabrication with planar gate interconnect surface.
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Ohno Takio (Hyogo JPX), Semiconductor device including a local interconnection between an interconnection layer and an adjoining impurity region.
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Tsukamoto Masanori (Kanagawa JPX) Gocho Tetsuo (Kanagawa JPX), Semiconductor device with antireflection film.
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Jeng Shin-Puu (Plano TX), TiSi₂/TiN clad interconnect technology.
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이 특허를 인용한 특허 (35)

Geffken, Robert M.; Horak, David V.; Stamper, Anthony K., Contact capping local interconnect.
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Geffken, Robert M.; Horak, David V.; Stamper, Anthony K., Contact capping local interconnect.
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Ramkumar Subramanian ; Bhanwar Singh ; Bharath Rangarajan ; Michael K. Templeton, Developer soluble dyed BARC for dual damascene process.
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Nagase Kunihiko,JPX, Dry etching process and a fabrication process of a semiconductor device using such a dry etching process.
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Lyons Christopher F. ; Bell Scott A. ; Karlsson Olov, Gate pattern formation using a BARC as a hardmask.
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Ko, Kei-Yu, Gate stack structure.
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Armacost Michael ; Hoh Peter ; Wise Richard S. ; Yan Wendy, High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials.
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Wang Fei ; Kai James K. ; En William G., In-situ etch of multiple layers during formation of local interconnects.
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Chang Jung-Ho,TWX ; Chen Hsi-Chuan,TWX ; Lin Dahcheng,TWX, In-situ nitride and oxynitride deposition process in the same chamber.
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Hung Raymond ; Caulfield Joseph Patrick ; Ding Jian, Integrated self aligned contact etch.
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Jigish D. Trivedi, Local interconnect structures and methods for making the same.
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Trivedi, Jigish D., Local interconnect structures and methods for making the same.
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Migita, Tatsuo; Ezawa, Hirokazu; Iijima, Tadashi; Togasaki, Takashi, Manufacturing method of semiconductor apparatus and semiconductor apparatus.
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Bode,Christopher A.; Pasadyn,Alexander J.; Toprac,Anthony J.; Hewett,Joyce S. Oey; Peterson,Anastasia Oshelski; Sonderman,Thomas J.; Miller,Michael L., Method and apparatus for initializing tool controllers based on tool event data.
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Lee, Sung Kwon; Lee, Jae Young, Method for fabricating a fine pattern in a semiconductor device.
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Lin Hua-Tai,TWX ; Jeng Erik S.,TWX ; Yao Liang-Gi,TWX, Method for improving patterning of a conductive layer in an integrated circuit.
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Hui Angela T. ; Yang Wenge ; Sahota Kashmir ; Ramsbey Mark T. ; Pangrle Suzette K. ; Ngo Minh Van, Method for removing anti-reflective coating layer using plasma etch process after contact CMP.
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Hui Angela T. ; Yang Wenge ; Sahota Kashmir ; Ramsbey Mark T. ; Pangrle Suzette K. ; Ngo Minh Van, Method for removing anti-reflective coating layer using plasma etch process before contact CMP.
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Hsieh Hung-Chang,TWX ; Lin Hua-Tai,TWX ; Liaw Jhon-Jhy,TWX ; Lee Jin-Yuan,TWX, Method of forming a hole in the sub quarter micron range.
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Bamnolker, Hanna; Phatak, Prashant; Raghuram, Usha; Geha, Sam, Method of forming contact openings.
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Hsaio Tommy C. ; Ramsbey Mark T. ; Sun Yu, Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region.
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Kuroda, Takahiko, Method of manufacturing semiconductor device.
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Mori, Katsumi, Methods for fabricating semiconductor devices.
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Katsumi Mori JP, Methods for manufacturing semiconductor devices.
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Plat Marina V. ; Hao Ming-Yin, Minimization of line width variation in photolithography.
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Sharan Sujit ; Sandhu Gurtej S., Plasma deposition tool operating method.
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Donohoe Kevin G. ; Stocks Richard L., Plasma etching methods.
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Donohoe Kevin G. ; Stocks Richard L., Plasma etching methods.
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Miller, Sheri; Krishna, Vinay; Viswanathan, Sriram, Process for post contact-etch clean.
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Shrivastava Ritu, Self-aligned contacts for salicided MOS devices.
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Strobl Peter, Semiconductor manufacturing method.
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Huang Jenn Ming,TWX, Silicide and salicide on the same chip.
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Kamineni, Vimal K.; Xie, Ruilong; Miller, Robert, Silicide protection during contact metallization and resulting semiconductor structures.
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Chao-chueh Wu TW, Two step plasma etch using variable electrode spacing.
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Chen Bi-Ling,TWX ; Jerry Erik S.,TWX ; Lee Daniel Hao-Tien,TWX, Two-step etching process for forming self-aligned contacts.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] In-situ etch of BARC layer during formation of local interconnects 원문보기