초록 ▼

A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dime

A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

대표청구항 ▼

What is claimed is: 1. A method for etching a deep via in a substrate comprising the steps of: providing a substrate with at least one first layer on top of the substrate; depositing at least one first lithographic imaging layer on top of the first layer; forming a first pattern having a first diam

What is claimed is: 1. A method for etching a deep via in a substrate comprising the steps of: providing a substrate with at least one first layer on top of the substrate; depositing at least one first lithographic imaging layer on top of the first layer; forming a first pattern having a first diameter into the first lithographic imaging layer, wherein the first diameter is equal to a final aimed diameter of a deep via; transferring the first pattern into the first layer, whereby a patterned first layer having the first pattern is obtained; removing the first lithographic imaging layer; depositing at least one uniform polymer layer deposited on top of the patterned first layer, whereby the diameter of the first pattern is reduced to a second diameter smaller than the first diameter; etching the deep via in the substrate using the first pattern with the uniform polymer layer on top as a hard mask; and removing the first lithographic imaging layer and the uniform polymer layer. 2. The method according to claim 1, wherein the first layer is a protective layer. 3. The method according to claim 1, wherein the first layer is a sacrificial layer. 4. The method according to claim 1, wherein the deep via has a height to width ratio higher than about 5:1. 5. The method according to claim 1, wherein the deep via has a width of from 1 μm to 10 μm and a depth into the substrate of from 10 μm to 100 μm. 6. The method according to claim 1, wherein the deep via has a width of 5 μm and a depth of 50 μm. 7. The method according to claim 1, for use in a method of fabricating high aspect ratio vias for stacking semiconductor wafers in the three dimensional stacking of interconnect structures or stacking elements of devices in MEMS applications. 8. The method according to claim 1, wherein the first pattern and the second pattern have a difference of more than about 10% and less than about 20% in diameter. 9. The method according to claim 1, wherein the lithographic imaging layer is a resist layer with an anti-reflective coating. 10. The method according to claim 1, wherein the step of removing the lithographic imaging layer comprises using an O2/N2 comprising plasma followed by a wet clean. 11. The method according to claim 1, wherein the first layer on top of the substrate is a permanent first layer. 12. The method according to claim 11, wherein the permanent first layer is a Pre Metal Dielectric layer. 13. The method according to claim 11, wherein the permanent first layer on top of the substrate is a SiO2 layer. 14. The method according to claim 1, wherein the etching of the deep via in the substrate is performed in a passivation polymer type etch process using a fluor comprising plasma. 15. The method according to claim 14, wherein the passivation polymer type etch process uses a C4F8/SF6 comprising plasma and comprises alternating a deposition step followed by an etch step, wherein the alternating deposition and etch steps are repeated. 16. The method according to claim 15, wherein the deposition step is performed using a C4F8/SF6 comprising plasma having more than 95% C4F8. 17. The method according to claim 15, wherein the etch step is performed using a C4F8/SF6 comprising plasma having more than 95% SF6. 18. A method for etching a deep via in a substrate comprising the steps of: providing a substrate with at least one first layer on top of the substrate; depositing at least one first lithographic imaging layer on top of the first layer; forming a first pattern having a first diameter into the first lithographic imaging layer; expanding the first pattern in the first lithographic imaging layer by resist trimming, whereby a trimmed pattern is created; transferring the trimmed pattern into the first layer, whereby a patterned first layer having the first pattern is obtained; removing the first lithographic imaging layer; depositing at least one second lithographic imaging layer on top of the patterned first layer; forming, into the second lithographic imaging layer and coinciding with the first pattern, a second pattern having a second diameter, wherein the first diameter and the second diameter are equal to each other and smaller than a final aimed diameter of a deep via; etching the deep via in the substrate using the patterned second layer as a hard mask; and removing the second lithographic imaging layer. 19. The method according to claim 18, wherein the resist trimming is performed in an O2 comprising plasma further comprising at least one of Cl2 and HBr. 20. The method according to claim 18, for use in a method of fabricating high aspect ratio vias for stacking semiconductor wafers in the three dimensional stacking of interconnect structures or stacking elements of devices in MEMS applications. 21. The method according to claim 18, wherein the deep via has a width of from 1 μm to 10 μm and a depth into the substrate of from 10 μm to 100 μm. 22. The method according to claim 18, wherein the step of removing the lithographic imaging layer comprises using an O2/N2 comprising plasma followed by a wet clean. 23. The method according to claim 18, wherein the etching of the deep via in the substrate is performed in a passivation polymer type etch process using a fluor comprising plasma. 24. A method for etching a deep via in a silicon substrate comprising the steps of: providing a silicon substrate with at least one first layer on top of the silicon substrate; depositing at least one first lithographic imaging layer on top of the first layer; forming a first pattern having a first diameter into the first lithographic imaging layer; transferring the first pattern into the first layer, whereby a patterned first layer having the first pattern is obtained; removing the first lithographic imaging layer; depositing at least one second lithographic imaging layer on top of the patterned first layer; forming, into the second lithographic imaging layer and coinciding with the first pattern, a second pattern having a second diameter; etching a deep via in the silicon substrate using the patterned second layer as a hard mask; and removing the second lithographic imaging layer. 25. The method according to claim 24, for use in a method of fabricating high aspect ratio vias for stacking semiconductor wafers in the three dimensional stacking of interconnect structures or stacking elements of devices in MEMS applications. 26. A method for etching a deep via in a silicon substrate, comprising the steps of: providing a silicon substrate with at least one first layer on top of the silicon substrate; depositing at least one lithographic imaging layer resist on top of the first layer; forming a resist pattern in the lithographic imaging layer resist with a target dimension smaller than a final aimed diameter of the deep via; transferring the resist pattern into the first layer; etching a deep via in the silicon substrate using the lithographic imaging layer resist as a hard mask, whereby an undercut is created under the first layer; trimming the resist pattern to the final aimed diameter of the deep via, isotropically removing an overhanging part of the first layer; to the final aimed diameter of the deep via; and removing the lithographic imaging layer resist. 27. The method according to claim 26, wherein the first layer is a protective layer. 28. The method according to claim 26, wherein the first layer is a sacrificial layer. 29. The method according to claim 26, wherein the deep via has a height to width ratio higher than about 5:1. 30. The method according to claim 26, wherein the deep via has a width of from 1 μm to 10 μm and a depth into the substrate of from 10 μm to 100 μm. 31. The method according to claim 26, wherein the deep via has a width of 5 μm and a depth of 50 μm. 32. The method according to claim 26, for use in a method of fabricating high aspect ratio vias to be used for stacking semiconductor wafers, in the three dimensional stacking of interconnect structures or stacking elements of devices in MEMS applications. 33. The method according to claim 26, wherein the resist pattern has a difference of more than about 10% and less than about 20% in diameter compared to the final aimed diameter of the deep via. 34. The method according to claim 26, wherein the lithographic imaging layer resist comprises an anti-reflective coating. 35. The method according to claim 26, wherein the resist trimming is performed in an O2 comprising plasma further comprising at least one of Cl2 and HBr. 36. The method according to claim 26, wherein the step of removing the lithographic imaging layer resist comprises using a O2/N2 comprising plasma followed by a wet clean. 37. The method according to claim 26, wherein the first layer on top of the substrate is a permanent first layer. 38. The method according to claim 37, wherein the permanent first layer is a Pre Metal Dielectric layer. 39. The method according to claim 37, wherein the permanent first layer on top of the substrate is a SiO2 layer. 40. The method according to claim 26, wherein the etching of the deep via in the substrate is performed in a passivation polymer type etch process using a fluor comprising plasma. 41. A method according to claim 40, wherein the passivation polymer type etch process uses a C4F8/SF6 comprising plasma and comprises alternating a deposition followed by an etch step, wherein the alternating deposition and etch steps are repeated. 42. A method according to claim 41, wherein the deposition step is performed using a C4F8/SF6 comprising plasma having more than 95% C4F8. 43. A method according to claim 41, wherein the etch step is performed using a C4F8/SF6 comprising plasma having more than 95% SF6.