[특허]Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application

[미국특허] Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/4763 H01L-021/3205 H01L-021/28 H01L-021/44
출원번호	US-0165003 (1998-10-01)
발명자 / 주소	Lim Chong Wee,SGX Pey Kin Leong,SGX Siah Soh Yun,SGX Lim Eng Hwa,SGX Chan Lap
출원인 / 주소	National University of Singapore, SGX
대리인 / 주소	Saile
인용정보	피인용 횟수 : 25 인용 특허 : 6

초록 ▼

A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in a silicon substrate 10. A gate oxide layer is formed on device areas. A doped blanket polysilicon layer 16 is formed on the gate oxide layer. A cap layer 20 composed of silicon nitride is formed on the polysilicon layer 16. The cap layer 20 and the polysilicon layer 16 are patterned by photoresist masking and anisotropic etching to form a bottom gate electrode 16A and a gate cap 20A. Lightly doped source/drain areas 22 are formed adjacent to the gate bottom electrodes 16A by ion implantation. Sidewall spacers 21 are formed on the gate electrode 16A and gate cap 20A. Source/drain regions 24 are formed by ion implantation adjacent to said sidewall spacers 21. A metal silicide 23 is formed on the source/drain regions 24. An interlevel dielectric layer (ILD) 28 is deposited and planarized by CMP using the gate cap 20A as a CMP stop. The gate cap 20 is selectively removed. A barrier layer 32 composed of a TaN, CoWP, TiN or W.sub.x N.sub.y is formed over the planarized IDL 28A. A top gate layer 36 composed of copper or tungsten is formed on the barrier layer 32. The top gate layer 36 and the barrier layer 32 are removed down to the level of the top of the ILD 28 using CMP; thereby forming a top gate electrode. A passivation layer 40, composed of Pd or NiP is selectively deposited over the gate top electrode 36A.

대표청구항 ▼

[ What is claimed is:] [1.] A method for fabricating an ultra-low sheet resistance gate electrode for CMOS applications; comprising the steps of:a) providing a semiconductor substrate having a gate oxide layer thereon, a bottom gate electrode over said gate oxide layer, a gate cap over said bottom gate electrode, a lightly doped source/drain region adjacent to said bottom gate electrode, sidewall spacers on said bottom gate electrode and said gate cap, source/drain regions adjacent to said sidewall spacers, suicide contacts on said source/drain regions, and an interlevel dielectric layer over said substrate, said gate oxide layer, said bottom gate electrode, said lightly doped source/drain region, said sidewall spacers, said source/drain regions, and said silicide contacts;b) chemical/mechanically polishing said interlevel dielectric layer down to the level of the top of said gate cap;c) selectively removing said gate cap;d) forming a barrier layer over said interlevel dielectric layer, said bottom gate electrode and said sidewall spacers;e) forming a top gate electrode layer on said barrier layer; said top gate electrode layer being composed of metal;f) removing said top gate electrode layer and said barrier layer down to the level of the top of said interlevel dielectric layer using chemical/mechanical polishing; thereby forming a gate electrode comprising a top gate electrode, a barrier layer and a bottom gate electrode;g) forming a passivation layer over said top gate electrode.

이 특허에 인용된 특허 (6)

Tigelaar Howard L. (Allen TX) Haken Roger A. (Dallas TX) Holloway Thomas C. (Dallas TX) Groover ; III Robert (Dallas TX), Integrated circuit process with TiN-gate transistor.
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Grivna Gordon (565 W. Laguna Azul Mesa AZ 85210) Bernhardt Bruce A. (4166 W. Orchid La. Chandler AZ 85226) Keller Gerald (841 Santa Ana St. Chandler AZ 85224), Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish.
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Bai Gang ; Fraser David B., Method of forming a polycide film.
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Wong Harianto,SGX ; Pey Kin Leong,SGX ; Chan Lap, Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance.
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Kwon Chul-soon,KRX, Methods of fabricating copper interconnects for integrated circuits.
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Kato Juri (Suwa JPX) Tanaka Kazuo (Suwa JPX), Semiconductor device having a gate electrode having a low dopant concentration.
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이 특허를 인용한 특허 (25)

Narasimha,Shreesh; O'Neil,Patricia A., CMOS device integration for low external resistance.
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Gardner Mark I. ; Fulford ; Jr. H. Jim ; May Charles E., Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures.
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Jacques Bertrand ; George Kluth ; Minh Van Ngo ; Christy Mei-Chu Woo, Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface.
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Matsuki, Takeo; Shinmura, Toshiki, Field effect transistor having a two layered gate electrode.
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Kim, Tae Kyun; Jang, Se Aug; Cha, Tae Ho; Yeo, In Seok, Method for fabricating a dual metal gate for a semiconductor device.
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Kim Seon Soon,KRX ; Choi Jun Gi,KRX, Method for fabricating a semiconductor device.
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Daubenspeck, Timothy H.; Landers, William F.; Zupanski-Nielsen, Donna S., Method for fabricating last level copper-to-C4 connection with interfacial cap structure.
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Huang, Jenn Ming, Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers.
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Wang,Gin Jei; Peng,Chao Hsien; Wu,Chii Ming; Chang,Chih Wei; Shue,Shau Lin, Method for forming a semiconductor device.
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Cabral, Jr., Cyril; Kedzierski, Jakub T.; Ku, Victor; Lavoie, Christian; Narayanan, Vijay; Steegen, An L., Method for integration of silicide contacts and silicide gate metals.
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Ying, Chentsau; Chen, Xiaoyi; Nallan, Padmapani C.; Kumar, Ajay, Method for removing residue from a magneto-resistive random access memory (MRAM) film stack using a dual mask.
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Mark Michael ; Jon D. Cheek, Method of fabricating a deep source/drain.
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See Alex,SGX ; Chan Lap ; Sundaresan Ravi, Method of forming contact to polysilicon gate for MOS devices.
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Pey Kin-Leong,SGX ; Ho Chaw Sing,SGX ; Chan Lap, Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process.
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Ming-Hsing Tsai TW; Chii-Ming Wu TW, Poly resistor structure for damascene metal gate.
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Ibok Effiong, Self-aligned damascene gate formation with low gate resistance.
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Ibok Effiong ; Rouse Richard P., Self-aligned damascene gate with contact formation.
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Wang,Gin Jie; Peng,Chao Hsien; Wu,Chii Ming; Chang,Chih Wei; Shue,Shau Lin, Semiconductor device and fabrication method thereof.
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[미국특허] Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application 원문보기