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Circuit and method for conditioning flash memory array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-016/04
출원번호 US-0344316 (1999-06-24)
발명자 / 주소
  • Chen Kou-Su
  • Fu Shih-Chun,TWX
  • Chan Jui-Te,TWX
출원인 / 주소
  • AMIC Technology, Inc.
대리인 / 주소
    Law +
인용정보 피인용 횟수 : 99  인용 특허 : 6

초록 ▼

A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages

대표청구항 ▼

[ What is claimed is:] [1.] A method of preventing over-erasure of a flash cell in a memory arras from an erase operation, said method comprising:(a) generating a plurality of separate conditioning signals in a predetermined time sequence, wherein a magnitude of said separate plurality of conditioni

이 특허에 인용된 특허 (6)

  1. Chen Kou-Su ; Liu David K. Y., Circuit and method for erasing flash memory array.
    상세보기
  2. Kobayashi Shinichi (Hyogo JPX) Terada Yasushi (Hyogo JPX) Nakayama Takeshi (Hyogo JPX) Miyawaki Yoshikazu (Hyogo JPX) Futatsuya Tomoshi (Hyogo JPX), Electrically erasable and programmable non-volatile memory device and a method of operating the same.
    상세보기
  3. Nobukata Hiromi,JPX, Flash EEPROM with erase verification and address scrambling architecture.
    상세보기
  4. Kato Yasushi (Tokyo JPX), Non-volatile semiconductor memory capable of erase- verifying memory cells in a test mode using a defective count circui.
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  5. Noguchi Kenji (Hyogo JPX), Nonvolatile semiconductor memory device and manufacturing method and testing method thereof.
    상세보기
  6. Korsh George J. ; Khan Sakhawat M., Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell.
    상세보기

이 특허를 인용한 특허 (99)

  1. Sommer, Naftali; Shalvi, Ofir; Perlmutter, Uri; Golov, Oren; Gurgi, Eyal; Anholt, Micha; Sokolov, Dotan, Adaptive estimation of memory cell read thresholds.
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  2. Shalvi, Ofir; Sommer, Naftali; Kasorla, Yoav, Adaptive over-provisioning in memory systems.
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  3. Shalvi, Ofir; Sokolov, Dotan, Automatic defect management in memory devices.
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  4. Meir, Avraham, Cache memory for hybrid disk drives.
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  5. Shalvi, Ofir; Sommer, Naftali; Maislos, Ariel; Sokolov, Dotan, Combined distortion estimation and error correction coding for memory devices.
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  6. Sokolov, Dotan; Sommer, Naftali, Command interface for memory devices.
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  7. Shalvi, Ofir; Sommer, Naftali, Compensation for voltage drifts in analog memory cells.
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  8. Sommer, Naftali; Anholt, Micha; Golov, Oren; Perlmutter, Uri; Winter, Shai; Semo, Gil, Data scrambling schemes for memory devices.
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  9. Shalvi, Ofir; Winter, Shai; Sommer, Naftali; Sokolov, Dotan, Data storage in analog memory cell arrays having erase failures.
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  10. Kasorla, Yoav; Sommer, Naftali; Gurgi, Eyal; Anholt, Micha, Data storage in analog memory cells across word lines using a non-integer number of bits per cell.
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  11. Meir, Avraham; Anholt, Micha; Sommer, Naftali; Gurgi, Eyal, Data storage in analog memory cells using a non-integer number of bits per cell.
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  12. Winter, Shai; Shalvi, Ofir, Data storage in analog memory cells using modified pass voltages.
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  13. Winter, Shai; Shalvi, Ofir, Data storage using modified voltages.
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  14. Shalvi, Ofir; Sokolov, Dotan; Gurgi, Eyal; Golov, Oren; Sommer, Naftali, Data storage with incremental redundancy.
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  15. Sommer, Naftali; Perlmutter, Uri, Database of memory read thresholds.
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  16. Shalvi, Ofir; Sommer, Naftali; Gurgi, Eyal; Maislos, Ariel, Distortion estimation and cancellation in memory devices.
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  17. Shalvi, Ofir; Sommer, Naftali; Gurgi, Eyal; Maislos, Ariel, Distortion estimation and cancellation in memory devices.
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  18. Shalvi, Ofir; Sommer, Naftali; Gurgi, Eyal; Maislos, Ariel, Distortion estimation and cancellation in memory devices.
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  19. Kasorla, Yoav; Gurgi, Eyal; Sokolov, Dotan; Shalvi, Ofir, Efficient data storage in multi-plane memory devices.
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  20. Shalvi, Ofir, Efficient data storage in storage device arrays.
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  21. Perlmutter, Uri; Kasorla, Yoav; Golov, Oren, Efficient interference cancellation in analog memory cell arrays.
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  22. Perlmutter, Uri; Sommer, Naftali; Shalvi, Ofir, Efficient re-read operations from memory devices.
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  23. Perlmutter, Uri; Sokolov, Dotan; Shalvi, Ofir; Golov, Oren, Efficient readout from analog memory cells using data compression.
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  24. Sommer, Naftali; Perlmutter, Uri; Sokolov, Dotan; Gurgi, Eyal, Efficient readout schemes for analog memory cell devices.
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  25. Sommer, Naftali; Perlmutter, Uri, Efficient readout schemes for analog memory cell devices using multiple read threshold sets.
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  26. Meir, Avraham; Shachar, Michael, Efficient selection of memory blocks for compaction.
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  27. Hemink,Gerrit Jan; Kamei,Teruhiko, Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage.
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  28. Hemink, Gerrit Jan; Kamei, Teruhiko, Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells.
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  29. Hemink,Gerrit Jan; Kamei,Teruhiko, Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells.
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  30. Higashitani,Masaaki, Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells.
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  31. Anholt, Micha; Ordentlich, Or; Sommer, Naftali; Shalvi, Ofir, Error correction coding over multiple memory pages.
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  32. Perlmutter, Uri; Winter, Shai; Gurgi, Eyal; Golov, Oren; Anholt, Micha, Estimation of memory cell read thresholds by sampling inside programming level distribution intervals.
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  33. Perlmutter, Uri; Winter, Shai; Gurgi, Eyal; Golov, Oren; Anholt, Micha, Estimation of memory cell read thresholds by sampling inside programming level distribution intervals.
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  34. Shalvi, Ofir; Sommer, Naftali; Gurgi, Eyal; Golov, Oren; Sokolov, Dotan, Estimation of non-linear distortion in memory devices.
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  35. Wang, Hsingya A.; Chou, Kai-Cheng; Rabkin, Peter, Flash memory cell erase scheme using both source and channel regions.
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  36. Shalvi, Ofir; Sommer, Naftali; Dar, Ronen; Anholt, Micha, Interference-aware assignment of programming levels in analog memory cells.
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  37. Shalvi, Ofir; Sokolov, Dotan; Maislos, Ariel; Cohen, Zeev; Gurgi, Eyal; Semo, Gil, Memory Device with adaptive capacity.
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  38. Shalvi, Ofir; Sommer, Naftali, Memory cell readout using successive approximation.
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  39. Sokolov, Dotan; Sommer, Naftali; Shalvi, Ofir; Perlmutter, Uri, Memory device with internal signap processing unit.
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  40. Perlmutter, Uri; Shalvi, Ofir; Kasorla, Yoav; Sommer, Naftali; Sokolov, Dotan, Memory device with multiple-accuracy read commands.
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  41. Shalvi, Ofir, Memory device with negative thresholds.
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  42. Shalvi, Ofir, Memory device with negative thresholds.
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  43. Sokolov, Dotan; Semo, Gil; Shalvi, Ofir, Memory device with reduced reading latency.
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  44. Meir, Avraham; Sommer, Naftali; Gurgi, Eyal, Memory device with reduced sense time readout.
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  45. Rotbard, Barak; Meir, Avraham, Memory management for unifying memory cell conditions by using maximum time intervals.
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  46. Meir, Avraham; Golov, Oren, Memory management schemes for non-volatile memory devices.
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  47. Shachar, Michael; Rotbard, Barak; Golov, Oren; Perlmutter, Uri; Sokolov, Dotan; Vlaiko, Julian; Schwartz, Yair, Memory system including a controller and processors associated with memory devices.
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  48. Yasuaki Hirano JP, Method for erasing data from a non-volatile semiconductor memory device.
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  49. Ito,Fumitoshi, Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory.
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  50. Ito, Fumitoshi, Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects.
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  51. Toros, Zeynep; Terzioglu, Esin; Siksek, Ahmad O.; Winograd, Gil I.; Anvar, Ali, Non-volatile memory apparatus and method capable of controlling the quantity of charge stored in memory cells.
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  52. Keays, Brady L., Non-volatile memory with block erase.
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  53. Shiino, Yasuhiro; Kouno, Daisuke; Irieda, Shigefumi; Nakai, Kenri; Takahashi, Eietsu, Non-volatile semiconductor storage device.
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  54. Shiino, Yasuhiro; Kouno, Daisuke; Irieda, Shigefumi; Nakai, Kenri; Takahashi, Eietsu, Non-volatile semiconductor storage device.
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  55. Shiino, Yasuhiro; Kouno, Daisuke; Irieda, Shigefumi; Nakai, Kenri; Takahashi, Eietsu, Non-volatile semiconductor storage device.
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  56. Shiino, Yasuhiro; Kouno, Daisuke; Irieda, Shigefumi; Nakai, Kenri; Takahashi, Eietsu, Non-volatile semiconductor storage device.
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  57. Shiino, Yasuhiro; Kouno, Daisuke; Irieda, Shigefumi; Nakai, Kenri; Takahashi, Eietsu, Non-volatile semiconductor storage device.
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  58. Shiino, Yasuhiro; Kouno, Daisuke; Irieda, Shigefumi; Nakai, Kenri; Takahashi, Eietsu, Non-volatile semiconductor storage device.
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  59. Shiino, Yasuhiro; Kouno, Daisuke; Irieda, Shigefumi; Nakai, Kenri; Takahashi, Eietsu, Nonvolatile semiconductor memory device using write pulses with different voltage gradients.
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  60. Shalvi, Ofir, Optimized selection of memory chips in multi-chips memory devices.
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  61. Sommer, Naftali, Parameter estimation based on error correction code parity check equations.
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  62. Ito,Fumitoshi, Partitioned soft programming in non-volatile memory.
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  63. Haque,Rezaul; Udeshi,Darshak, Program-verify sensing for a multi-level cell (MLC) flash memory device.
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  64. Perlmutter, Uri; Shalvi, Ofir, Programming analog memory cells for reduced variance after retention.
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  65. Shalvi, Ofir; Gurgi, Eyal; Perlmutter, Uri; Golov, Oren, Programming orders for reducing distortion in arrays of multi-level analog memory cells.
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  66. Shalvi, Ofir; Sommer, Naftali; Sokolov, Dotan; Kasorla, Yoav, Programming schemes for multi-level analog memory cells.
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  67. Jones, Mason, Programming to mitigate memory cell performance differences.
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  68. Jones, Mason, Programming to mitigate memory cell performance differences.
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  69. Sommer, Naftali, Read commands for reading interfering memory cells.
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  70. Dar, Ronen; Gurgi, Eyal; Anholt, Micha; Sommer, Naftali, Read threshold setting based on soft readout statistics.
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  71. Anholt, Micha, Reading analog memory cells using built-in multi-threshold commands.
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  72. Sommer, Naftali; Shalvi, Ofir; Sokolov, Dotan, Reading memory cells using multiple thresholds.
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  73. Sommer, Naftali; Shalvi, Ofir; Sokolov, Dotan, Reading memory cells using multiple thresholds.
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  74. Sommer, Naftali; Shalvi, Ofir; Sokolov, Dotan, Reading memory cells using multiple thresholds.
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  75. Isachar, Ori; Vlaiko, Julian; Semo, Gil; Levy, Atai, Reducing peak current in memory systems.
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  76. Sommer, Naftali; Shalvi, Ofir, Reducing programming error in memory devices.
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  77. Shalvi, Ofir; Cohen, Zeev, Reduction of back pattern dependency effects in memory devices.
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  78. Shalvi, Ofir; Sommer, Naftali; Perlmutter, Uri; Vlaiko, Julian; Neerman, Moshe; Schwartz, Yair; Maislos, Ariel, Redundant data storage in multi-die memory systems.
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  79. Shalvi, Ofir; Sommer, Naftali; Perlmutter, Uri; Vlaiko, Julian; Neerman, Moshe, Redundant data storage schemes for multi-die memory systems.
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  80. Rotbard, Barak; Sommer, Naftali; Winter, Shai; Shalvi, Ofir; Sokolov, Dotan; Ordentlich, Or; Anholt, Micha, Rejuvenation of analog memory cells.
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  81. Shalvi, Ofir, Reliable data storage in analog memory cells in the presence of temperature variations.
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  82. Shalvi, Ofir; Sommer, Naftali; Rotbard, Barak; Golov, Oren; Anholt, Micha; Perlmutter, Uri, Reliable data storage in analog memory cells subjected to long retention periods.
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  83. Salomon, Tavi; Shalvi, Ofir; Shachar, Michael; Golov, Oren, Reuse of host hibernation storage space by memory controller.
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  84. Shalvi, Ofir; Rotbard, Barak; Golov, Oren; Anholt, Micha; Perlmutter, Uri, Segmented data storage.
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  85. Sokolov, Dotan; Sommer, Naftali; Perlmutter, Uri; Shalvi, Ofir, Selective activation of programming schemes in analog memory cell arrays.
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  86. Sommer, Naftali; Perlmutter, Uri; Winter, Shai, Selective re-programming of analog memory cells.
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  87. Combe,Marylene; Daga,Jean Michel, Self-adaptive program delay circuitry for programmable memories.
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  88. Hemink,Gerrit Jan; Kamei,Teruhiko, Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells.
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  89. Shalvi, Ofir; Sommer, Naftali; Perlmutter, Uri; Sokolov, Dotan, Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N.
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  90. Toros, Zeynep; Terzioglu, Esin; Siksek, Ahmad O.; Winograd, Gil I.; Anvar, Ali, System and method for controlling logical value and integrity of data in memory systems.
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  91. Ito,Fumitoshi, System for partitioned erase and erase verification in a non-volatile memory to compensate for capacitive coupling.
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  92. Hemink, Gerrit Jan; Kamei, Teruhiko, Systems for erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage.
    상세보기
  93. Hemink,Gerrit Jan; Kamei,Teruhiko, Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells.
    상세보기
  94. Higashitani,Masaaki, Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells.
    상세보기
  95. Ito, Fumitoshi, Systems for partitioned soft programming in non-volatile memory.
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  96. Hemink,Gerrit Jan; Kamei,Teruhiko, Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells.
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  97. Sokolov, Dotan; Rotbard, Barak, Use of host system resources by memory controller.
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  98. Wan, Jun; Lutze, Jeffrey W; Pang, Chan Sui, Word line compensation in non-volatile memory erase operations.
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  99. Wan,Jun; Lutze,Jeffrey W.; Pang,Chan Sui, Word line compensation in non-volatile memory erase operations.
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