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A NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a partic

A NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.

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1. A NAND flash memory core with multi-level row decoding comprising: a NAND memory cell array comprising a plurality of sectors each sector having a plurality of columns and a plurality of rows;a global row decoder that performs a first level of row decoding for all of the sectors;for each sector,

1. A NAND flash memory core with multi-level row decoding comprising: a NAND memory cell array comprising a plurality of sectors each sector having a plurality of columns and a plurality of rows;a global row decoder that performs a first level of row decoding for all of the sectors;for each sector, a corresponding local row decoder that performs a second level of row decoding only for that sector;wherein the plurality of sectors consists of n sectors, and the NAND flash memory core is configured to:execute first read and program operations for a selected single sector; andexecute second read and program operations in parallel for a selected plurality of sectors up to all n of the sectors. 2. The NAND flash memory core of claim 1 wherein: the NAND memory cell array comprises a plurality of blocks, each block comprising a plurality of rows, each row comprising memory cells of each of the sectors;the global row decoder performs row decoding to select one block from the plurality of blocks. 3. The NAND flash memory core of claim 2 configured to perform read and program operations to a resolution of one row within one sector, and to perform erase operations to a resolution of one block within one sector. 4. The NAND flash memory core of claim 1 wherein: the plurality of sectors of the NAND memory cell array and local row decoders are arranged in a layout that alternates between local row decoder and corresponding sector of the NAND memory cell array. 5. The NAND flash memory core of claim 1 further comprising: for each sector, a corresponding page buffer circuit. 6. The NAND flash memory core of claim 1 further comprising: for each sector, a corresponding page decoder. 7. The NAND flash memory core of claim 1 further comprising: for each sector, a corresponding column decoder. 8. The NAND flash memory core of claim 1 further comprising: connections between the global row decoder and the local row decoders that comprise a plurality of blocklines that are each commonly connected to each local row decoder. 9. The NAND flash memory core of claim 8 wherein the global row decoder comprises: a plurality of block decoders each commonly connected to block decoder lines, each block decoder connected to one of the plurality of blocklines. 10. The NAND flash memory core of claim 9 further comprising: a block pre-decoder that receives an address or portion of an address, and generates a block decoder output on the block decoder lines;the global row decoder comprising a plurality of block decoders commonly connected to the block decoder lines. 11. The NAND flash memory core of claim 1 further comprising: for each local row decoder, connections between the local row decoder and the NAND memory cell array that comprise a plurality of wordlines, each wordline connecting the local row decoder to memory cells of an associated row in the corresponding sector. 12. The NAND flash memory core of claim 1 further comprising: for each sector, a corresponding page decoder connected to the local row decoder of that sector through page decoder lines. 13. The NAND flash memory core of claim 12 wherein each local row decoder comprises a plurality of sector decoders, wherein the sector decoders of a given local row decoder are commonly connected to the page decoder lines of the page decoder for that sector. 14. The NAND flash memory core of claim 1 wherein: the NAND flash memory core is configured to execute the first read and program operations for the selected single sector by:the global row decoder performing the first level of row decoding to select a subset of the plurality of rows;the corresponding local row decoder of the selected single sector performing the second level of row decoding to select a row within the subset of the plurality of rows selected by the global row decoder; andthe NAND flash memory core is configured to execute the second read and program operations in parallel for the selected plurality of sectors up to all n of the sectors by:the global row decoder performing the first level of row decoding to select a subset of the plurality of rows, andfor each sector of the selected plurality of sectors, the corresponding local row decoder of the sector performing the second level of row decoding to select a row within the subset of the plurality of rows selected by the global row decoder. 15. A NAND flash memory core with multi-level row decoding comprising: a NAND memory cell array comprising a plurality of sectors each sector having a plurality of columns and a plurality of rows;a global row decoder that performs a first level of row decoding for all of the sectors;for each sector, a corresponding local row decoder that performs a second level of row decoding only for that sector;for each sector, a corresponding page decoder;page decoder lines connecting each page decoder to the corresponding local row decoder;wherein the NAND flash memory core is configured to execute first read and program operations for a selected single sector by:the global row decoder performing a first level of row decoding to select a subset of the plurality of rows;the page decoder of the selected single sector receiving an address or portion of an address, and generating a page decoder output on the page decoder lines;the corresponding local row decoder of the selected single sector performing the second level of row decoding to select a row within the subset of the plurality of rows selected by the global row decoder as a function of the page decoder output;for the first read and program operations, reading includes transferring contents of the selected row of the selected sector into the corresponding page buffer circuit,and programming includes transferring contents of the corresponding page buffer circuit to the selected row of the selected sector;to execute second read and program operations in parallel for a selected plurality of sectors up to all n of the sectors, the global row decoder performing a first level of row decoding to select a subset of the plurality of rows, and for each sector of the selected plurality of sectors:the page decoder of the sector receiving an address or portion of an address, and generating a page decoder output on the page decoder lines;the corresponding local row decoder of the sector performing the second level of row decoding to select a row within the subset of the plurality of rows selected by the global row decoder as a function of the page decoder output;for the second read and program operations, reading includes transferring contents of the selected row of the sector into the corresponding page buffer circuit,and programming includes transferring contents of the corresponding page buffer circuit to the selected row of the sector. 16. A NAND flash memory core with multi-level row decoding comprising: a NAND memory cell array comprising a plurality of sectors each sector having a plurality of columns and a plurality of rows;a global row decoder that performs a first level of row decoding for all of the sectors;for each sector, a corresponding local row decoder that performs a second level of row decoding only for that sector;the NAND memory cell array comprises a plurality of blocks, each block comprising a plurality of rows, each row comprising memory cells of each of the sectors;the global row decoder performs row decoding to select one block from the plurality of blocks;execute a first erase for a selected block within a selected single sector; andexecute a second erase for a selected block in parallel for a selected plurality of sectors up to all n of the sectors. 17. A method comprising: in a NAND flash memory core, performing multi-level row decoding,the method for use in the NAND flash memory core comprising a NAND memory cell array comprising a plurality of sectors, each sector having a plurality of columns and a plurality of rows, the method comprising:performing a first level of row decoding for all of the sectors;performing a second level of decoding for at least one sector;the method for use in the NAND flash memory core comprising a plurality of blocks, each block comprising a plurality of rows, each row comprising memory cells of each of the sectors, wherein:performing a first level of row decoding comprises performing row decoding to select one block from the plurality of blocks;the method for use in the NAND flash memory core in which the plurality of sectors consists of n sectors, the method further comprising:performing first read and program operations to a resolution of one row within one sector for a selected single sector; andperforming second read and program operations to a resolution of one row within one sector in parallel for a selected plurality of sectors up to all n of the sectors. 18. A method comprising: in a NAND flash memory core, performing multi-level row decoding,the method for use in the NAND flash memory core comprising a NAND memory cell array comprising a plurality of sectors, each sector having a plurality of columns and a plurality of rows, the method comprising:performing a first level of row decoding for all of the sectors;performing a second level of decoding for at least one sector;the method for use in the NAND flash memory core comprising a plurality of blocks, each block comprising a plurality of rows, each row comprising memory cells of each of the sectors, wherein:performing a first level of row decoding comprises performing row decoding to select one block from the plurality of blocks comprising:performing first read and program operations for a selected single sector by:performing the first level of row decoding to select a subset of the plurality of rows;performing the second level of row decoding to select a row within the selected subset of the plurality of rows; andperforming second read and program operations in parallel for a selected plurality of sectors up to all n of the sectors by:the global row decoder performing the first level of row decoding to select a subset of the plurality of rows, andfor each sector of the selected plurality of sectors, performing the second level of row decoding to select a row within the selected subset of the plurality of rows. 19. A device comprising: a NAND flash memory core with multi-level row decoding, the NAND flash memory core including memory cell array sectors, and the NAND flash memory core being configured to:execute first programming for a selected single memory cell array sector; andexecute second programming in parallel for a selected plurality of memory cell array sectors up to all n of the sectors. 20. The device of claim 19 wherein the NAND flash memory core further includes a global row decoder that performs a first level of row decoding for all of the n memory cell array sectors, the NAND flash memory core further including, for each memory cell array sector, a corresponding local row decoder that performs a second level of row decoding only for that sector. 21. The device of claim 20 wherein the n memory cell array sectors and local row decoders are arranged in a layout that alternates between local row decoder and corresponding memory cell array sector of the NAND flash memory core. 22. The device of claim 19 further comprising: for each memory cell array sector, a corresponding page buffer circuit. 23. The device of claim 19 further comprising: for each memory cell array sector, a corresponding page decoder. 24. The device of claim 19 further comprising: for each memory cell array sector, a corresponding column decoder.