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A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher threshold voltage devices in other po

A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher threshold voltage devices in other portions of the gate (e.g., precharge circuitry). This use of dual threshold voltage devices minimizes power consumption while maximizing speed. During standby mode, the gate is operated in an evaluation mode to substantially mitigate standby current.

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What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. A logic gate, comprising: an evaluation unit having first and second pairs of inputs, said evaluation unit performing a logic operation on said first and second pairs and outputting a first pair of outp

What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. A logic gate, comprising: an evaluation unit having first and second pairs of inputs, said evaluation unit performing a logic operation on said first and second pairs and outputting a first pair of outputs during an evaluation mode; an inverter coupled to and inverting said first pair of outputs and outputting a second pair of outputs corresponding to said inverted first pair of outputs; and first and second precharge units, said first precharge unit being configured to precharge the first pair of outputs to a first predetermined voltage level during a precharge mode, and the second precharge unit being configured to precharge the second pair of outputs to a second predetermined voltage level during the precharge mode. 2. The logic gate of claim 1, further comprising: first and second latches, said latches being respectively configured to hold the values of the first and second pairs of outputs during the evaluation mode. 3. The logic gate of claim 2, wherein said latches are configured to allow said first and second pairs of outputs to float during a standby mode. 4. The logic gate of claim 2, wherein said latches comprise a pair of cross-coupled transistors, and said logic gate further comprises first and second enable gates for enabling said first and second latches in response to first and second latching control signals. 5. The logic gate of claim 1, wherein said evaluation unit is active when the logic gate is in a standby mode. 6. The logic gate of claim 1, wherein said first pair of inputs comprises a first complementary pair of inputs and said second pair of inputs comprises a second complementary pair of inputs. 7. The logic gate of claim 6, wherein said first pair of outputs comprises a first complementary pair of outputs and said second pair of outputs comprises a second complementary pair of outputs. 8. The logic gate of claim 1, wherein said logic operation is an exclusive-OR operation. 9. The logic gate of claim 1, wherein said logic operation is a NOR operation. 10. The logic gate of claim 1, wherein said logic operation is a NAND operation. 11. The logic gate of claim 1, wherein said first precharge unit comprises a first equalization network and said second precharge unit comprises a second equalization network. 12. The logic gate of claim 11, wherein said first equalization circuit comprises a first network of at least three transistors configured to pull one output of said first pair of outputs to a logic level of the other output of said first pair of outputs during the precharge mode. 13. The logic gate of claim 12, wherein said second equalization circuit comprises a second network of at least three transistors configured to pull one output of said second pair of outputs to a logic level of the other output of said second pair of outputs during the precharge mode. 14. The logic gate of claim 13, wherein the transistors in the first and second networks operate at a first threshold voltage and transistors in said evaluation unit operate at a second, different threshold voltage. 15. The logic gate of claim 1, wherein said inverter, said precharge units and said evaluation unit reside in the same integrated circuit. 16. A processor system comprising: a processor; and a circuit comprising a logic gate coupled to said processor, said logic gate comprising: an evaluation unit having first and second pairs of inputs, said evaluation unit performing a logic operation on said first and second pairs and outputting a first pair of outputs during an evaluation mode, an inverter coupled to and inverting said first pair of outputs and outputting a second pair of outputs corresponding to said inverted first pair of outputs, and first and second precharge units, said first precharge unit being configured to precharge the first pair of outputs to a first predetermined voltage level during a precharge mode, and the second precharge unit being configured to precharge the second pair of outputs to a second predetermined voltage level during the precharge mode. 17. The system of claim 16, wherein said logic gate further comprises: first and second latches, said latches being respectively configured to hold the values of the first and second pairs of outputs during the evaluation mode. 18. The system of claim 17, wherein said latches are configured to allow said first and second pairs of outputs to float during a standby mode. 19. The system of claim 17, wherein said latches comprise a pair of cross-coupled transistors, and said logic gate further comprises first and second enable gates for enabling said first and second latches in response to first and second latching control signals. 20. The system of claim 16, wherein said evaluation unit is active when the logic gate is in a standby mode. 21. The system of claim 16, wherein said first pair of inputs comprises a first complementary pair of inputs and said second pair of inputs comprises a second complementary pair of inputs. 22. The system of claim 21, wherein said first pair of outputs comprises a first complementary pair of outputs and said second pair of outputs comprises a second complementary pair of outputs. 23. The system of claim 16, wherein said logic operation is an exclusive-OR operation. 24. The system of claim 16, wherein said logic operation is a NOR operation. 25. The system of claim 16, wherein said logic operation is a NAND operation. 26. The system of claim 16, wherein said first precharge unit comprises a first equalization network and said second precharge unit comprises a second equalization network. 27. The system of claim 26, wherein said first equalization circuit comprises a first network of at least three transistors configured to pull one output of said first pair of outputs to a logic level of the other output of said first pair of outputs during the precharge mode. 28. The system of claim 27, wherein said second equalization circuit comprises a second network of at least three transistors configured to pull one output of said second pair of outputs to a logic level of the other output of said second pair of outputs during the precharge mode. 29. The system of claim 28, wherein the transistors in the first and second networks operate at a first threshold voltage and transistors in said evaluation unit operate at a second, different threshold voltage. 30. The system of claim 16, wherein said inverter, said precharge units and said evaluation unit reside in the same integrated circuit. 31. A method of operating a logic gate, said method comprising the acts of: precharging first and second pairs of outputs during a precharge mode; inputting first and second pairs of input during an evaluation mode; performing a logic operation on the first and second pairs of inputs to create a new first pair of outputs during the evaluation mode; inverting the new first pair of outputs to generate a new second pair of outputs; and floating at least one of the first and second pairs of outputs during a standby mode of operation. 32. The method of claim 31, further comprising the act of latching the new first and second pairs of outputs. 33. The method of claim 31, wherein the logic operation is an exclusive-OR operation. 34. The method of claim 31, wherein the logic operation is a NAND operation. 35. The method of claim 31, wherein the logic operation is a NOR operation. 36. The method of claim 31, wherein said precharging act comprises equalizing the first pair of outputs to a first logic level and equalizing the second pair of outputs to a second logic level. 37. The method of claim 36, wherein said act of equalizing the first pair of outputs comprises setting one output of said first pair of outputs to a logic level of the other of said first pair of outputs. 38. The method of claim 36, wherein said act of equalizing the second pair of outputs comprises setting one output of said second pair of outputs to a logic level of the other of said second pair of outputs. 39. The method of claim 31 further comprising the act of floating the first and second pairs of outputs during a standby mode of operation. 40. A method of fabricating a logic gate in an integrated circuit, said method comprising the integrated circuit fabrication acts of: fabricating an evaluation unit having first and second pairs of inputs, said evaluation unit performing a logic operation on said first and second pairs and outputting a first pair of outputs during an evaluation mode; fabricating an inverter coupled to and inverting said first pair of outputs and outputting a second pair of outputs corresponding to said inverted first pair of outputs; and fabricating first and second precharge units, said first precharge unit being configured to precharge the first pair of outputs to a first predetermined voltage level during a precharge mode, and the second precharge unit being configured to precharge the second pair of outputs to a second predetermined voltage level during the precharge mode. 41. The method of claim 40, further comprising the act of fabricating first and second latches, said latches being respectively configured to hold the values of the first and second pairs of outputs during the evaluation mode. 42. The method of claim 41, wherein said act of fabricating the latches comprises the acts of: fabricating first and second pairs of cross-coupled transistors; and fabricating first and second enable gates for enabling said first and second pair of cross-coupled transistors in response to first and second latching control signals. 43. The method of claim 40, wherein said act of fabricating the first and second precharge units comprises fabricating a first equalization network and a second equalization network.