초록 ▼

A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns.

A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit. This greatly reduces the testing time, allows for greater amount of data to be obtained which improves the statistically accuracy, and reduces costs as well.

대표청구항 ▼

What is claimed is: 1. A method for testing Time Dependent Dielectric Breakdowns (TDDBs) of metal-oxide-semiconductor (MOS) capacitor dielectric films using a TDDB test pattern, the method comprising: providing a plurality of unit test pattern cells between a first node and a second node, each of t

What is claimed is: 1. A method for testing Time Dependent Dielectric Breakdowns (TDDBs) of metal-oxide-semiconductor (MOS) capacitor dielectric films using a TDDB test pattern, the method comprising: providing a plurality of unit test pattern cells between a first node and a second node, each of the unit test pattern cells including a fuse coupled between the first node and a third node, a MOS capacitor coupled between the third node and a ground, and a MOS transistor coupled between the ground and the second node, wherein a gate of the MOS transistor is coupled to the third node; applying a first voltage to the first node and applying a second voltage to the second node and providing an ammeter between the second node and a second voltage supplying unit that supplies the second voltage; and measuring a total drain current using the ammeter. 2. A method as claimed in claim 1, wherein the MOS transistor is an N type when the MOS capacitor is the N type. 3. A method as claimed in claim 2, wherein the first voltage is higher than zero (0) volt when the MOS transistor and the MOS capacitor are the N type. 4. A method as claimed in claim 1, wherein the MOS transistor is an N type when the MOS capacitor is a P type. 5. A method as claimed in claim 4, wherein the first voltage is lower than zero (0) volt when the MOS transistor is the N type while the MOS capacitor is the P type.