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Method of manufacturing dummy gates in gate last process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/3205
출원번호 US-0510730 (2011-11-30)
등록번호 US-8541296 (2013-09-24)
우선권정보 CN-2011 1 0257658 (2011-09-01)
국제출원번호 PCT/CN2011/002001 (2011-11-30)
§371/§102 date 20120518 (20120518)
국제공개번호 WO2013/029210 (2013-03-07)
발명자 / 주소
  • Yang, Tao
  • Zhao, Chao
  • Yan, Jiang
  • Li, Junfeng
  • Lu, Yihong
  • Chen, Dapeng
출원인 / 주소
  • The Institute Of Microelectronics Chinese Academy of Science
인용정보 피인용 횟수 : 1  인용 특허 : 34

초록

The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask p

대표청구항

1. A method of manufacturing a dummy gate in a gate last process, which comprises the following steps: forming a dummy gate material layer and a hard mask material layer sequentially on a substrate;etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; anddry etchin

이 특허에 인용된 특허 (34)

  1. Thomas C. Scholer ; Allen S. Yu ; Paul J. Steffan, Controlled gate length and gate profile semiconductor device.
  2. Scholer, Thomas C.; Yu, Allen S.; Steffan, Paul J., Controlled gate length and gate profile semiconductor device and manufacturing method therefor.
  3. Offenhäusser, Andreas; Odenthal, Margarete; Goryll, Michael; Moers, Jürgen; Lüth, Hans, Fet sensor with specially configured gate electrode for the highly sensitive detection of analytes.
  4. Satoh Shinichi,JPX ; Ozaki Hiroji,JPX ; Eimori Takahisa,JPX, Field effect transistor with a shaped gate electrode.
  5. Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew V.; Datta, Suman; Shah, Uday; Chau, Robert S., Forming integrated circuits with replacement metal gate electrodes.
  6. Sakata, Masanori, Insulated gate type field effect transistor having a silicon gate electrode.
  7. Sakai ; Tetsushi ; Sakakibara ; Yutaka ; Murota ; Junichi ; Wada ; Tsuto mu, Insulated gate type field effect transistors.
  8. Yu Allen S. ; Cheung Patrick K. ; Steffan Paul J., LDD transistor using novel gate trim technique.
  9. Iguchi Katsuji,JPX ; Azuma Kenichi,JPX ; Kawamura Akio,JPX, MOS transistor and fabrication process therefor.
  10. Murakami Kouji (Tokyo JPX) Matsunaga Taira (Yokohama JPX), MOS type semiconductor device and method for manufacturing the same.
  11. Naoki Mukoyama JP, Magnetoresistive read head having reduced barkhausen noise.
  12. Subrahmanyam Chivukula,SGX ; Pradeep Yelehanka Ramachandramurthy,SGX ; Rajagopal Ramakrishnan,SGX, Method for forming a T-gate for better salicidation.
  13. Lee Joo-Hyung,KRX ; Hong Mun-Pyo,KRX ; Youn Chan-Joo,KRX ; Jung Byung-Hoo,KRX ; Hwang Chang-Won,KRX, Method for forming a TFT in a liquid crystal display.
  14. Hong, Zhongshan, Method for forming a gate electrode.
  15. Yu Allen S. ; Cheung Patrick K. ; Steffan Paul J., Method for forming graded LDD transistor using controlled polysilicon gate profile.
  16. Sun, Sam X., Method of creating photolithographic structures with developer-trimmed hard mask.
  17. Nakamura Moritaka (Yokohama JPX) Kurimoto Takashi (Hashima JPX) Iizuka Katsuhiko (Kawasaki JPX), Method of dry etching with hydrogen bromide or bromide.
  18. Ishikawa,Akira, Method of fabricating semiconductor device.
  19. Michael Mark W. ; Dawson Robert ; Fulford ; Jr. H. Jim ; Gardner Mark I. ; Hause Frederick N. ; Moore Bradley T. ; Wristers Derick J., Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls.
  20. Taniguchi Akihisa (Itami JPX), Method of making field effect transistor with T-shaped gate electrode.
  21. Lund Clarence A. (Mesa AZ) Barron Edward W. (Mesa AZ) Holstin Howard E. (Tempe AZ) Sugino Michael D. (Scottsdale AZ), Method of making self-aligned device.
  22. Kevin R. Lensing ; James Broc Stirton, Method of using scatterometry measurements to determine and control gate electrode profiles.
  23. Ju Byong-sun,KRX ; Kim Hyoun-woo,KRX ; Kang Chang-jin,KRX ; Moon Joo-tae,KRX ; Nam Byeong-yun,KRX, Methods of etching platinum group metal film and forming lower electrode of capacitor.
  24. Matsui Shigekazu (Tokyo JPX) Kgaya Kenichi (Tokyo JPX) Ushida Masao (Tokyo JPX) Maruyama Kouichi (Tokyo JPX), Photo-mask blank comprising a shading layer having a variable etch rate.
  25. Owen ; III William H. (Sunnyvale CA) Steele Charles H. R. (Santa Clara CA) Pashley Richard D. (Mountain View CA), Process for defining polycrystalline silicon patterns.
  26. Liu Sheau-Ming S. (Los Altos CA), Process for forming metal plated regions and lines in MOS circuits.
  27. Owyang Jon ; Aronowitz Sheldon ; Kimball James P., Process for forming re-entrant geometry for gate electrode of integrated circuit structure.
  28. Brintzinger,Axel; Trovarelli,Octavio; Leiberg,Wolfgang, Process for producing layer structures for signal distribution.
  29. Shah,Uday; Barns,Chris E.; Doczy,Mark L.; Brask,Justin K.; Kavalieros,Jack; Metz,Matthew V.; Chau,Robert S., Replacement gate process for making a semiconductor device that includes a metal gate electrode.
  30. Sugiyama,Koichi; Takao,Yoshihiro; Sugatani,Shinji; Matsunaga,Daisuke; Wada,Takayuki; Fujita,Tohru; Kokura,Hikaru, Semiconductor device and method of manufacturing the same.
  31. Hovel, Harold J.; Woodall, Jerry M., Semiconductor device fabrication.
  32. Jecmen Robert M. (Sunol CA), Shadow masking process for forming source and drain regions for field-effect transistors and like regions.
  33. Nam, Seung Hee, Thin film transistor substrate and method for fabricating the same.
  34. William J. Taylor, Jr. ; Srikanth B. Samavedam ; Nigel Cave, Transistor with shaped gate electrode and method therefor.

이 특허를 인용한 특허 (1)

  1. Ho, Wei-Shuo; Chiang, Tsung-Yu; Chen, Kuang-Hsin, Metal gate structure and manufacturing method thereof.
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