As semiconductor has become multifunctionalised, there were increasing needs for more number of pins, as well as packaging that suits subminiature package for the possible application in the area of mobile, wearable, etc.. However, due to the fact that wafer level package (WLP) uses fan-in level...
As semiconductor has become multifunctionalised, there were increasing needs for more number of pins, as well as packaging that suits subminiature package for the possible application in the area of mobile, wearable, etc.. However, due to the fact that wafer level package (WLP) uses fan-in level method placing I/O connector at the inner part of the chip, thereby creating limit to creating configuration and confronting multi chip package (MCP). The fan-out wafer level package (FOWLP) has emerged as a new technology. FOWLP technology is able to produce cheaper and thinner semiconductor package than current printed circuit board (PCB) type package. FOWLP is constituted of epoxy mold compound (EMC) and semiconductor chip. FOWLP can be created thinner and at cheaper price because it generates re-distribution layer (RDL) and solder ball itself, which eliminates its original printed circuit board. In addition, with RDL, not only it can create both high integration and high function package, but also it can confront system in package (SiP) which constitutes multiple chip in single package. Wafer deformation is core technology task happening from coefficient of expansion (CTE) mismatch per each material during FOWLP process because fan-out wafer is consisted of EMC basis and is easily deformed due to thermal stresses and moisture absorptions. Die drift occurred from wafer expansion and shrinkage makes overlay abnormal and loss of electrical test yield. The objective of this thesis is to choose the compatible EMC for FOWLP through major property analysis, and defines the primary cause of die drift phenomenon from the wafer expansion and shrinkage. Also, by defining the factor of die drift variation in wafer level, this thesis presents a optimized method about die drift variation. Based on my experimental results, it was confirmed that wafer was shrunk during pre-mold cure. Also it was expanded during post-mold cure and staging on the room temperature. The primary cause for shrinkage during pre-mold cure was defined by evaporation of solvent inside EMC according to the property analysis result of EMC. Considering that expansion during post-mold cure is related to CTE of EMC, expansion during staging on room temperature is related to moisture absorption from the air. Suitable temperature for pre-mold cure is defined as 103 ± 2~3℃ to minimize the wafer shrinkage during this cure process. The die drift variation according to ±5℃ of temperature variation during post-mold cure was very small. When storage condition of wafer was in vacuum sealing or N2 chamber, wafer expansion did not occurred. Then, when saturated wafer was in pre-bake from moisture absorption, wafer expansion is able to be compensated. After optimizing the factors related to wafer deformation, it was confirmed that die drift variation level is improved when it was from ±40um to ±15um level.
As semiconductor has become multifunctionalised, there were increasing needs for more number of pins, as well as packaging that suits subminiature package for the possible application in the area of mobile, wearable, etc.. However, due to the fact that wafer level package (WLP) uses fan-in level method placing I/O connector at the inner part of the chip, thereby creating limit to creating configuration and confronting multi chip package (MCP). The fan-out wafer level package (FOWLP) has emerged as a new technology. FOWLP technology is able to produce cheaper and thinner semiconductor package than current printed circuit board (PCB) type package. FOWLP is constituted of epoxy mold compound (EMC) and semiconductor chip. FOWLP can be created thinner and at cheaper price because it generates re-distribution layer (RDL) and solder ball itself, which eliminates its original printed circuit board. In addition, with RDL, not only it can create both high integration and high function package, but also it can confront system in package (SiP) which constitutes multiple chip in single package. Wafer deformation is core technology task happening from coefficient of expansion (CTE) mismatch per each material during FOWLP process because fan-out wafer is consisted of EMC basis and is easily deformed due to thermal stresses and moisture absorptions. Die drift occurred from wafer expansion and shrinkage makes overlay abnormal and loss of electrical test yield. The objective of this thesis is to choose the compatible EMC for FOWLP through major property analysis, and defines the primary cause of die drift phenomenon from the wafer expansion and shrinkage. Also, by defining the factor of die drift variation in wafer level, this thesis presents a optimized method about die drift variation. Based on my experimental results, it was confirmed that wafer was shrunk during pre-mold cure. Also it was expanded during post-mold cure and staging on the room temperature. The primary cause for shrinkage during pre-mold cure was defined by evaporation of solvent inside EMC according to the property analysis result of EMC. Considering that expansion during post-mold cure is related to CTE of EMC, expansion during staging on room temperature is related to moisture absorption from the air. Suitable temperature for pre-mold cure is defined as 103 ± 2~3℃ to minimize the wafer shrinkage during this cure process. The die drift variation according to ±5℃ of temperature variation during post-mold cure was very small. When storage condition of wafer was in vacuum sealing or N2 chamber, wafer expansion did not occurred. Then, when saturated wafer was in pre-bake from moisture absorption, wafer expansion is able to be compensated. After optimizing the factors related to wafer deformation, it was confirmed that die drift variation level is improved when it was from ±40um to ±15um level.
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