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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. TE, 전문기술교육, v.39 no.3, 2002년, pp.1 - 7
조정환 (金浦大學 電子情報系列) , 정정화 (漢陽大學校 電子電氣컴퓨터工學部)
This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead z...
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