[논문]Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity

Sharma, Sudhansh; Kumar, Pawan

doi:10.5573/jsts.2009.9.3.136

Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity 원문보기

Journal of semiconductor technology and science, v.9 no.3, 2009년, pp.136 - 147

Sharma, Sudhansh (Department of Information Technology and Systems Sciences, Vishveshwarya School of Business Management (VSBM)) , Kumar, Pawan (Department of Physics, M.M.H. College (Affiliated to C.C.S. University Meerut))

Abstract ▼ AI-Helper

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

주제어

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문제 정의

in SOI devices. In this work, we highlight the usefulness of underlap channel profile to suppress short channel effects in GOI based SG/DG MOSFETs. Optimal design guidelines are proposed for 25 nm underlap channel single/double gate SOI/GOI MOSFETs to suppress SCEs based on the ratio of effective channel length to natural/characteristic length.

제안 방법

In this paper, we use the expression of effective channel length for gate-source/drain underlap devices and natural/characteristic length scale for sin믾e and double gate SOI/GOI MOSFETs to evaluate the design criterion to suppress SCEs. Our earlier work [29] high lightted the usefulness of lateral S/D doping gradient

후속연구

Reasonable values of S-slope and DIBL can be achieved in underlap channel GOI DG devices. Results presented in this work will be useful in design and optimization of nanoscale single and double gate SOI/GOI MOSFETs for low voltage applications.

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