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NTIS 바로가기Journal of semiconductor technology and science, v.9 no.3, 2009년, pp.136 - 147
Sharma, Sudhansh (Department of Information Technology and Systems Sciences, Vishveshwarya School of Business Management (VSBM)) , Kumar, Pawan (Department of Physics, M.M.H. College (Affiliated to C.C.S. University Meerut))
In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effe...
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International technology roadmap for semiconductor 2006 edition. Available from: (http://public.itrs.net)
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