It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled d...
It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.
It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.
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제안 방법
In this paper, it has been implemented by co-work designing both the NAND flash memory and the dedicated NAND controller for a high reliability and high speed IO. The Moving read using virtual negative read algorithm and randomization is proposed to make it a high reliability.
성능/효과
The Moving read using virtual negative read algorithm and randomization is proposed to make it a high reliability. As a result, fail bit ratio is significantly improved 70% and the randomized pattern data avoids the worst pattern and that fail bit count improves from 700 bits to 6 bits. Furthermore, the NAND chip size is reduced because of implementing those methods in the dedicated controller.
There are lots of issues related to interference caused by adjacent programmed cells and fringing field, disturbance caused by excessive channel boosting, floating node charge loss tolerance, charge trapping caused by floating shrink and write performance degradation following more the number of program pulses around sub-20 nm node. [3] Providing that both a NAND Flash memory and the dedicated NAND controller are packaged into one-chip to overcome scaling issue and high performance, and then there exist the large consumption of operating current and the bottle neck data path between interfaces using the embedded algorithm which is applied with SoC architecture.
참고문헌 (3)
K. Takeuchi et al, "Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)," IEEE J. Solid-State Circuits, Vol.44, pp.1227-1234, 2009.
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