Na, Kyoung Il
(Convergence Components & Materials Research Laboratory, ETRI)
,
Kim, Sang Gi
(Convergence Components & Materials Research Laboratory, ETRI)
,
Koo, Jin Gun
(Convergence Components & Materials Research Laboratory, ETRI)
,
Kim, Jong Dae
(Convergence Components & Materials Research Laboratory, ETRI)
,
Yang, Yil Suk
(Convergence Components & Materials Research Laboratory, ETRI)
,
Lee, Jin Ho
(Convergence Components & Materials Research Laboratory, ETRI)
In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi-superjunction (semi-SJ) trench double-diffused MOSFET (TDMOS). In this new process, the thick single insulation layer ($SiO_2$) of a conventional device is replaced by a multilayered insulator ($SiO_2/...
In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi-superjunction (semi-SJ) trench double-diffused MOSFET (TDMOS). In this new process, the thick single insulation layer ($SiO_2$) of a conventional device is replaced by a multilayered insulator ($SiO_2/SiN_x/TEOS$) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on-resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on-resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on-resistance are 108 V and $1.1m{\Omega}cm^2$, respectively.
In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi-superjunction (semi-SJ) trench double-diffused MOSFET (TDMOS). In this new process, the thick single insulation layer ($SiO_2$) of a conventional device is replaced by a multilayered insulator ($SiO_2/SiN_x/TEOS$) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on-resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on-resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on-resistance are 108 V and $1.1m{\Omega}cm^2$, respectively.
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제안 방법
In this letter, we proposed nitride_RSO, which is a new fabrication process of an RSO power device with an inserted nitride layer in the thick insulator region. In addition, simulation using a TCAD simulator was performed to compare the electrical properties of a conventional RSO TDMOS to those of a nitride_RSO TDMOS with various cell pitch sizes and insulator thicknesses. Moreover, a nitride_RSO TDMOS device was successfully fabricated, and its BVDS and RON,SPEC were 108 V and 1.
대상 데이터
For medium voltage operation, this device is designed with a 4-μm cell pitch, 1.5-μm gate width, 6-μm trench depth, 50-nm gate oxide, and 500-nm-thick insulator layer.
참고문헌 (12)
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W. Saito et al., "High Breakdown Voltage (>1000 V) Semi-Superjunction MOSFETs Using 600-V Class Superjunction MOSFET Process," IEEE Trans. Electron Devices, vol. 52, no. 10, Oct. 2005, pp. 2317-2322.
Y. Miura, H. Ninomiya, and K. Kobayashi, "High Performance Superjunction UMOSFETs with Split P-Columns Fabricated by Multi-Ion-Implantations," Proc. ISPSD, 2005, pp. 39-42.
S. Yamauchi et al., "Fabrication of High Aspect Ratio Doping Region by Using Trench Filling of Epitaxial Si Growth," Proc. ISPSD, 2001, pp. 363-366.
T. Minato et al., "Which Is Cooler, Trench or Muiti-Epitaxy? Cutting-Edge Approach for the Silicon Limit by the Super Trench Power MOS-FET (STM)," Proc. ISPSD, 2000, pp. 73-76.
E. Napoli, H. Wang, and F. Udrea, "The Effect of Charge Imbalance on Superjunction Power Devices: An Exact Analytical Solution," IEEE Electron Device Lett., vol. 29, no. 3, Mar. 2008, pp. 249-251.
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