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Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes 원문보기

Journal of semiconductor technology and science, v.14 no.6, 2014년, pp.824 - 831  

Kim, Youngmin (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST)) ,  Lee, Jaemin (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST)) ,  Ryu, Myunghwan (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST))

Abstract ▼ AI-Helper 아이콘AI-Helper

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) a...

주제어

#Double Patterning Lithography (DPL)   #Triple Patterning Lithography (TPL)   #Litho-etch litho-etch (LELE)   #Multipatterning   #Interconnect Variation   #RC Delay  

AI 본문요약
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제안 방법

  • 1. Cross-sectional view of the six lines of the metal 1 interconnect with the structural parameters used in the simulations (top) for DPL and (bottom) for TPL. Note that metal A is the result of under-etching, metal B is the result of over-etching, and metal C is the result of nominal etching.
  • In this paper, structural variations (e.g., the width or height) in metals and OL errors of the DPL and TPL processes are combined and comprehensively evaluated, and the performance impacts of the variations are analyzed by the propagation delay of the interconnect. In addition, the crosstalk noise impact due to the coupling capacitance between neighboring wires is investigated.
  • In this study, both DPL and TPL share the same structural patterns and variations assuming metal patterning in the 20-nm technology node (e.g., metal pitch = 60 nm). The TPL process, however, will be widely used for the 14-nm technology node and beyond [1, 6, 11].
  • In this study, the structural variations of metal interconnects and OL errors occurring with DPL and TPL processes are comprehensively evaluated. Possible parameters are tested to investigate the impact on performance.
  • In this study, the structural variations of metal interconnects and OL errors occurring with DPL and TPL processes are comprehensively evaluated. Possible parameters are tested to investigate the impact on performance. Propagation delays are measured to access the impact.
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참고문헌 (27)

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    상세보기 crossref

  3. K. Yuan, J. S. Yang, and D. Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization," IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 2, pp. 185-196, 2010. 

    상세보기 crossref

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  12. Q. Li, et al., "14nm M1 Triple Patterning," in Proc. of SPIE 8326, Optical Microlithography XXV, vol. 8326, pp. 1-7, 2012. 

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  20. R. S. Ghaida and P. Gupta, "Within-Layer Overlay Impact for Design in Metal Double Patterning," Semiconductor Manufacturing, IEEE Transactions on, vol. 23, no. 3, pp. 381-390, 2010. 

    상세보기 crossref

  21. Raphael reference manual, ver. H-2013.03, [Online]. Available: http://www.synopsys.com. 

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  25. P. Gupta, et al., "Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing," in Proc. of International VLSI/ULSI Multilevel Interconnection Conference, pp. 352-363, 2005. 

  26. J. Gambino, F. Chen, and J. He, "Copper Interconnect Technology for the 32 nm Node and Beyond," in Proc. of IEEE Custom Integrated Circuits Conference, pp. 141-148, 2009. 

  27. D. Sinha, J. Luo, S. Rajagopalan, and S. Batterywala, "Impact of Modern Process Technologies on the Electrical Parameters of Interconnects," in Proc. of International Conference on VLSI Design, pp. 875-880, 2007. 

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