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NTIS 바로가기Journal of semiconductor technology and science, v.14 no.6, 2014년, pp.824 - 831
Kim, Youngmin (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST)) , Lee, Jaemin (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST)) , Ryu, Myunghwan (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST))
In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) a...
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