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NTIS 바로가기한국CAD/CAM학회논문집 = Transactions of the Society of CAD/CAM Engineers, v.19 no.4, 2014년, pp.402 - 409
안의국 (아주대학교 산업공학과) , 서정철 (삼성전자) , 박상철 (아주대학교 산업공학과)
Presented in this paper is a scheduling method for semiconductor backend process considering the backward pegging. It is known that the pegging for frontend is a process of labeling WIP lots for target order which is specified by due date, quantity, and product specifications including customer info...
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핵심어 | 질문 | 논문에서 추출한 답변 |
---|---|---|
라미네이션 공정은 무엇인가? | 라미네이션(Lamination) 공정은 이물질로부터 웨이퍼를 보호하기 위해 보호 테이프를 웨이퍼에 붙이는 공정이고, 백그라인딩(Back Grinding) 공정은 웨이퍼 뒷면의 불필요한 막을 제거하는 공정으로, 두꺼운 뒷면을 깎아 저항을 줄이고 열전도율의 향상하는 공정으로 전자기기의 소형, 박형, 경량화를 위해 필요하다. 웨이퍼 절단(Sawing)은 반도체 전공정에서 만들어진 웨이퍼를 절단하여 개개의 칩으로분리하는 공정이다. | |
반도체 제조는 어떤 공정으로 나뉘는가? | 반도체 제조는 크게 전공정과 후공정으로 나뉘어 진다. 300개 이상의 단위 공정으로 구성된 전 공정은 절연체와 비 절연체의 패턴을 가공함으로써 웨이퍼 전자회로를 만들어간다[25]. | |
반도체 제조 과정 중 후공정은 어떻게 구분되는가? | 300개 이상의 단위 공정으로 구성된 전 공정은 절연체와 비 절연체의 패턴을 가공함으로써 웨이퍼 전자회로를 만들어간다[25]. 후공정은 웨이퍼가 완성된 이후 반도체 칩을 탑재될 기기에 적합한 형태로 만드는 공정을 의미하며 웨이퍼를 자르고 조립한 이후 테스트하고 출하하는 방식으로 진행된다. 후공정은 다시 칩을 조립하는 패키지 공정과 조립된 칩을 테스트하는 패키지 테스트공정으로 구분된다. 후공정 중 패키지 공정의 세부작업은 Fig. |
Lee, Y.H., Cho, H.M., Park, J.K. and Lee, B.K., 1999, Scheduling Simulator for Semiconductor Fabrication Line, IE Interface, 12(3), pp.437-447.
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Park, S.C., Kim, B.H., Seo, J.C., Ahn, E., Chung, Y. and Yang, K.-R., 2013, Fab Simulation with Recipe Arrangement of Tools, Proceedings of the 2013 Winter Simulation Conference.
Rose, O., 2003, Comparison of Due-date Oriented Dispatch Rules in Semiconductor Manufacturing, In Proceeding of the 2003 Industrial Engineering Research Conference.
Zhou, Z. and Rose, O. 2011. A Composite Rule Combining Due Date Control and WIP Balance in a Wafer FAB. In Proceedings of the 2011 Winter Simulation Conference.
GiBrau Mike and Rose, O., 2012, Development and Introduction of a Combined Dispatching Policy at a High-mix Low-volume ASIC Facility, Proceedings of the 2012 Winter Simulation Conference.
Zhou, Z. and Rose, O. 2012. WIP Control and Calibration in a Wafer FAB. In Proceedings of the 2012 Winter Simulation Conference.
Sivakumar, A.I. and Chong, C.S., 2001, A Simulation Based Analysis of Cycle Time Distribution, and Throughput in Semiconductor Backend Manufacturing, Computers in Industry, 45, pp.59-78.
Chai, J.I., 2008, A Case Study on the Throughput Improvement in the Semiconductor Package Process, Kyung Hee University, Master Degree Thesis.
Quadt, D., Simulation-based Scheduling of Parallel Wire-bonders with Limited Clamp&paddles, Proceedings of the 2006 Winter Simulation Conference.
Tovia, F., Mason, S.J. and Ramasami, B., 2004, A Scheduling Heuristic for Maximizing Wirebonder Thoughput, IEEE Transactions on Electronics Packaging Manufacturing, 27(2).
Jang, S.H., Whang, W.K., Park, S.K., Koh, R.B., Koo, Y.M. and Woo, K.B., 1999 Petri Nets Modeling and Dynamic Scheduling for the Backend Line in Semiconductor Manufacturing, International Journal of Control Robotics and Systems, 5(6), pp.724-733.
Hsu, H.P. and Su, C.T., 2005, The Implementation of an Activity-based Costing Collaborative Planning System for Semiconductor Backend Product, International Journal of Production Research, 43(12), pp.2473-2492.
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Lu, S.C.H., Ramaswamy, D. and Kumar, P.R., 1998, Efficient Scheduling Policies to Reduce Mean and Variance of Flow-Time in Semiconductor Manufacturing Plants, IEEE Transactions on Semiconductor Manufacturing, 7(3), pp.115-130.
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