[논문]Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs

Nguyen, H.V.; Kim, Youngmin

doi:10.5573/ieiespc.2016.5.1.10

Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs 원문보기

IEIE Transactions on Smart Processing and Computing, v.5 no.1, 2016년, pp.10 - 16

Nguyen, H.V. (Hardware Design Group, Viettel R&D Institute) , Kim, Youngmin (Department of Computer Engineering, Kwangwoon University)

Abstract ▼ AI-Helper

In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).

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문제 정의

However, to the best of our knowledge, a FinFET-based digital voltage sensor has yet to be developed. In this study, the unique characteristics of FinFET devices are examined to develop a novel design for a FinFET-based digital voltage sensor. By exploiting the ability to independently control the two gates of a ptype FinFET (p-FinFET) in low-power mode, a voltage-totime mechanism that effectively controls the propagation delay of clock input is presented.

제안 방법

To overcome these barriers, trigate FinFETs with separate gate controllability and reduced leakage are a promising substitute for CMOS devices. Accordingly, this paper describes a method of using FinFET devices in the design of a fully digital voltage sensor.
In the LPIG CDE, the FinFET maintains low power consumption while its front and back gates are controlled by independent voltage sources. For this study, the LPIG CDE is applied to a digital voltage sensor to sense the input voltage in the range 0.7V to 1.1V at a high conversion rate (100 MHz).
The major additions to that work are: (1) more in-depth and accurate double-gate FinFET controllable delay element (CDE) investigation, (2) voltage and process variation analysis, and (3) power consump-tion–related analysis and comparisons with other designs.
1 V and a 50-mV resolution was proposed. The performance of this sensor under voltage and process variations was evaluated using SPICE simulations. The simulation results confirm that the proposed voltage sensor can operate at ultra-low power consumption and a fairly high frequency with high linearity.
The LPIG mode of the p-FinFET was discussed thoroughly in Section 3. To confirm whether the lowpower mode of the FinFET device is maintained within LPIG mode, the power consumption levels of the various voltage sensors were assessed. Table 2 compares the proposed sensor with other design techniques.
Table 2 compares the proposed sensor with other design techniques. To the best of our knowledge, this design is the first approach using double-gate FinFET devices to develop an ADC. Although the other processes shown in Table 2 are not quite compatible, their measured power consumptions are significantly high.

성능/효과

The performance of this sensor under voltage and process variations was evaluated using SPICE simulations. The simulation results confirm that the proposed voltage sensor can operate at ultra-low power consumption and a fairly high frequency with high linearity.

참고문헌 (18)

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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs 원문보기

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Low-Power Fully Digital Voltage Sensor using 32-nm FinFETs 원문보기

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