최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기마이크로전자 및 패키징 학회지 = Journal of the Microelectronics and Packaging Society, v.24 no.1, 2017년, pp.35 - 43
윤태식 (한국과학기술원 기계공학과) , 김택수 (한국과학기술원 기계공학과)
The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV ...
* AI 자동 식별 결과로 적합하지 않은 문장이 있을 수 있으니, 이용에 유의하시기 바랍니다.
핵심어 | 질문 | 논문에서 추출한 답변 |
---|---|---|
3차원 적층된 칩의 장점은? | 최근 고 집적회로를 만들기 위하여, 칩을 3차원으로 적층하는 방법이 활발히 연구 및 적용 되고 있다. 이러한 3차원 적층된 칩의 경우, 단위 면적당 집적도를 적층 수에 비례하여 올릴 수 있으며, 전기적으로는 칩 간의 인터커넥션 길이가 짧아지게 되어 신호 및 전력의 효율적인 전달이 가능하다. 칩의 3차원 적층을 위하여 와이어 본딩1,2), 플립 칩3,4) side termination5) 등의 기술을 사용하며, 최근에는 TSV(Through Silicon Via)기술이 주목받고 있으며 중점적으로 개발되고 있다. | |
칩의 3차원 적층에 사용되는 기술은? | 이러한 3차원 적층된 칩의 경우, 단위 면적당 집적도를 적층 수에 비례하여 올릴 수 있으며, 전기적으로는 칩 간의 인터커넥션 길이가 짧아지게 되어 신호 및 전력의 효율적인 전달이 가능하다. 칩의 3차원 적층을 위하여 와이어 본딩1,2), 플립 칩3,4) side termination5) 등의 기술을 사용하며, 최근에는 TSV(Through Silicon Via)기술이 주목받고 있으며 중점적으로 개발되고 있다. | |
비아가 형성된 칩 들을 3차원으로 적층하기 위한 접합 공정에는 어떤 접합이 적용되고 있는가? | 비아가 형성된 칩 들을 3차원으로 적층하기 위해서 접합 공정이 필요하다. 실리콘 산화물을 이용한 oxide 접합, 구리 및 주석을 이용한 metal-metal 접합, 고분자 접착제를 이용한 polymer 접합 등이 적용되고 있다. 칩의 박막화 시에는 Wet-etching, Grinding, CMP(Chemical Mechanical Polishing) 등의 기술이 적용된다. |
F. Carson, H. T. Lee, J. H. Yee, J. Punzalan, and E. Fontanilla, "Die to die copper wire bonding enabling low cost 3D packaging", 2011 IEEE 61st. ECTC, 1502, (2011).
K. M. Brown, "System in package 'the rebirth of SIP'", Proc. IEEE 2004 CICC, 681, (2004).
T. Iwasaki, M. Watanabe, S. Baba, Y. Hatanaka, S. Idaka, Y. Yokoyama, and M. Kimura, "Development of 30 micron pitch bump interconnections for COC-FCBGA", 2006 Proc. 56th. ECTC, 1216, (2006).
R. Chaware, K. Nagarajan, and S. Ramalingam, "Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer", 2012 IEEE 62nd. ECTC, 279, (2012).
K. D. Gann, "High density packaging of flash memory", Seventh Biennial IEEE Int. NVMT Confernce Proc., 96, (1998).
J. H. Lau, "Overview and outlook of through-silicon via (TSV) and 3D integrations", Microelectron. Int. 28, 8, (2011).
M. Motoyoshi, "Through-silicon via (TSV)", Proc. IEEE, 97, 43, (2009).
K. Takahashi, and M. Sekiguchi, "Through silicon via and 3- D wafer/chip stacking technology", 2006 Symp. VLSI Circuits Dig. Tech. Paper, 89, (2006).
P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland, B. Wunderle, B. Michel, and H. Reichl, "Through silicon via technology-processes and reliability for wafer-level 3D system integration", 2008 58th. ECTC, 841, (2008)
M. Park, S. Kim, and S. E. Kim, "TSV Liquid Cooling System for 3D Integrated Circuits", J. Microelectron. Packag. Soc., 20, 1, (2013).
J. V. Olmen, A. Mercha, G. Katti, C. Huyghebaert, J. V. Aelst, E. Seppala, Z. Chao, S. Armini, J. Vaes, R. C. Teixeira, M. V. Cauwenberghe, P. Verdonck, K. Verhemeldonck, A. Jourdain, W. Ruythooren, M. de P. de ten Broeck, A. Opdebeeck, T. Chiarella, B. Parvais, I. Debusschere, T. Y. Hoffmann, B. De Wachter, W. Dehaene, M. Stucchi, M. Rakowski, Ph. Soussan, R. Cartuyvels, E. Beyne, S. Biesemans, and B. Swinnen, "3D stacked IC demonstration using a through silicon via first approach", 2008 IEEE IEDM, 1, (2008).
U. Kang, H.-J. Chung, S. Heo, D.-H. Park, H. Lee, J. H. Kim, S.-H. Ahn, S.-H. Cha, J. Ahn, D. Kwon, J.-W. Lee, H.-S. Joo, W.-S. Kim, D. H. Jang, N. S. Kim, J.-H. Choi, T.-G. Chung, J.-H. Yoo, J. S. Choi, C. Kim, and Y.-H. Jun, "8 Gb 3-D DDR3 DRAM using through-silicon-via technology", IEEE J. Solid-State Circuits, 45, 111, (2010).
N. Khan, V. S. Rao, S. Lim, H. S. We, V. Lee, X. Zhang, E. B. Liao, R. Nagarajan, T. C. Chai, V. Kripesh, and J. H. Lau, "Development of 3-D silicon module with TSV for system in packaging", IEEE Trans. Compon. Packag. Technol., 33, 3, (2010).
S. Hu, Y.-Z. Xiong, L. Wang, R. Li, J. Shi, and T.-G. Lim, "Compact high-gain mmWave antenna for TSV-based system- in-package application" IEEE Trans. Compon. Packag. Manuf. Technol., 2, 841, (2012).
J.-S. Lim, J.-H. Kim, H.-J. Kim, J.-W. Jung, H. Lee, M.-Y. Park, and J.-S. Chae, "3D SDRAM Package Technology for a Satellite", J. Microelecton. Packag. Soc., 19(1), 25, (2012).
N. Ikegami, T. Yoshida, A. Kojima, H. Ohyi, N. Koshida, and M. Esashi, "Active-matrix nanocrystalline Si electron emitter array for massively parallel direct-write electron-beam system: first results of the performance evaluation", J. Micro/ Nanolith. MEMS MOEMS, 11, 031406-1, (2012).
B. Wu, A. Kumar, and S. Pamarthy, "High aspect ratio silicon etch: A review", J. Appl. Phys., 108, 051101-1, (2010).
Y. C. Tan, C. M. Tan, X. W. Zhang, T. C. Chai, and D. Q. Yu, "Electromigration performance of Through Silicon Via (TSV)-A modeling approach", Microelectron. Reliab., 50, 1336, (2010).
X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R. R. Tummala, and S. K. Sitaraman, "Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV)", 2009 59th. ECTC, 624, (2009).
C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K. W. Seah, K. Vaidyanathan, and T. C. Chai, "Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps", IEEE Trans. Adv. Packag., 32, 720, (2009).
X. Liu, Q. Chen, V. Sundaram, M. Simmons-Matthews, K. P. Wachtler, R. R. Tummala, and S. K. Sitaraman, "Thermomechanical behavior of through silicon vias in a 3D integrated package with inter-chip microbumps", 2011 IEEE 61st. ECTC, 1190, (2011).
N. Ranganathan, K. Prasad, N. Balasubramanian, and K. L. Pey, "A study of thermo-mechanical stress and its impact on through-silicon vias", J. Micromech. Microeng., 18, 075018, (2008).
M. A. Hopcroft, W. D. Nix, and T. W. Kenny, "What is the Young's Modulus of Silicon?", J. Microelectromech. Syst., 19, 229, (2010).
A. P. Karmarkar, X. Xu, and V. Moroz, "Performanace and reliability analysis of 3D-integration structures employing through silicon via (TSV)", 2009 IEEE Int. Rel. Phys. Symp., 682, (2009).
K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, "Thermo-mechanical reliability of 3-D ICs containing through silicon vias", 2009 59th. ECTC, 630, (2009).
B. Xie, X. Q. Shi, C. H. Chung, and S. W. R. Lee, "Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design", 2010 Proc. 60th. ECTC, 1166, (2010).
C. Okoro, J. W. Lau, F. Golshany, K. Hummler, and Y. S. Obeng, "A detailed failure analysis examination of the effect of thermal cycling on Cu TSV reliability", IEEE Trans. Electon Devices, 61, 15, (2014).
T. T. Chua, S. W. Ho, H. Y. Li, C. H. Khong, E. B. Liao, S. P. Chew, W. S. Lee, L. S. Lim, X. F. Pang, S. L. Kriangsak, C. Ng, S. Nathapong, and C. H. Toh, "3D interconnection process development and integration with low stress TSV", 2010 Proc. 60th. ECTC, 798, (2010).
M. Jung, J. Mitra, D. Z. Pan, and S. K. Lim, "TSV stressaware full-chip mechanical reliability analysis and optimization for 3D IC", Commun. ACM, 57, 107, (2014).
J. H. Lau, and T. G. Yue, "Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration systemin- package (SiP)", Microelecton. Reliab., 52, 2660, (2012).
J. H. Lau, and T. G. Yue, "Thermal management of 3D IC integration with TSV (through silicon via)", 2009 59th. ECTC, 635, (2009).
Z. Liu, S. Swarup, and S. X.-D. Tan, "Compact lateral thermal resistance modeling and characterization for TSV and TSV array", Proc. Int. Conference on Computer-Aided Design, 275, (2013).
H. Tanaka, and K.-S. Kim, "Introduction of reliability test technology for electronics package", J. Microelectron. Packag. Soc., 19, 1, (2012).
X. Liu, Q. Chen, V. Sundaram, R. R. Tummala, and S. K. Sitaraman, "Failure analysis of through-silicon vias in freestanding wafer under thermal-shock test", Microelectron. Reliab., 53, 70, (2013).
M. G. Farooq, T. L. Graves-Abe, W. F. Landers, C. Kothandaraman, B. A. Himmel, P. S. Andry, C. K. Tsang, E. Sprogis, R. P. Volant, K. S. Petrarca, K. R. Winstel, J. M. Safran, T. D. Sullivan, F. Chen, M. J. Shapiro, R. Hannon, R. Liptak, D. Berger, and S. S. Iyer, "3D copper TSV integration, testing and reliability", 2011 IEDM, 7.1.1, (2011).
P. Kumar, I. Dutta, and M. S. Bakir, "Interfacial effects during thermal cycling of Cu-filled through-silicon vias (TSV)", J. Electron. Mater., 41, 322, (2012).
C. Okoro, R. Labie, K. Vansteels, A. Franquet, M. Gonzalez, B. Vandevelde, E. Beyne, D. Vandepitte, and B. Verlinden, "Impact of the electrodeposition chemistry used for TSV filling on the microstructural and thermo-mechanical response of Cu", J. Mater. Sci., 46, 3868, (2011).
A. Jain, R. E. Jones, R. Chatterjee, S. Pozder, and Z. Huang, "Thermal modeling and design of 3D integrated circuits", 2008 11th. ITHERM, 1139, (2008).
K. H. Lee, “Application of Plating Simulation for PCB andPackaging Process”, J. Microelectron. Packag. Soc., 19(3), 1,(2012).
K.-S. Kim, D.-H. Choi, and S.-B. Jung, “Overview on thermalmanagement technology for high power device packaging”, J.Microelectron. Packag. Soc., 21(2), 13, (2014).
*원문 PDF 파일 및 링크정보가 존재하지 않을 경우 KISTI DDS 시스템에서 제공하는 원문복사서비스를 사용할 수 있습니다.
오픈액세스 학술지에 출판된 논문
※ AI-Helper는 부적절한 답변을 할 수 있습니다.