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12. M.-C. Sun, S. W. Kim, H. W. Kim, G. Kim, H. Kim, J.-H. Lee, H. Shin and B.-G. Park, "Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits", Jpn. J. Appl. Phys, Vol. 51, p. 04DC03, Apr. 2012. 

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13. O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions", IEEE Electron Device Lett, Vol. 29, No. 9, pp. 1074-1077, Sep. 2008. 

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19. K. Boucart and A. MIonescu, "Double-Gate Tunnel FET With High- ${\kappa}$ Gate Dielectric" IEEE Trans. Electron Devices, vol. 54, no. 7, Jul. 2007. 

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20. Ankur Beohar, Nandakishor Yadav and Santosh Kumar Vishvakarma, "Analysis of trap-assisted tunnelling in asymmetrical underlap 3D-cylindrical GAA-TFET based on hetero-spacer engineering for improved device reliability", IET Micro & Nano Lett, Vol. 12, Iss. 12, pp. 982-986, 2017. 

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21. H. T. Kwon, S. W. Kim, W. J. Lee, D. H. Wee, and Y. Kim, "A Recessed-channel Tunnel Field-Effect Transistor (RTFET) with the Asymmetric Source and Drain", Journal Of Semiconductor Technology and Sience, Vol. 16, No. 5, pp. 635-640, Oct. 2016. 

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22. S. W. Kim, W. Y. Choi, M.-C. Sun, H. W. Kim, and B.-G. Park, "Design Guideline of Si-Based LShaped Tunneling Field-Effect Transistors", Jpn. J. Appl. Phys, Vol. 51, p. 06FE09, Jun. 2012. 

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23. A. Ali, D. S. Seo and I. H. Cho, "Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate", J. Semicond. Technol. Sci, Vol. 17, No. 1, pp. 156-161, Feb. 2017. 

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