최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기Journal of semiconductor technology and science, v.18 no.3, 2018년, pp.360 - 366
Ji, Seunggyu (Department of Electronic Engineering, Myongji University) , Kim, Hyungtak (School of Electronic and Electrical Engineering, Hongik University) , Cho, Il Hwan (Department of Electronic Engineering, Myongji University)
A novel tunneling field effect transistor (TFET) with a recess channel is proposed. Proposed TFET has a thin intrinsic region and it is formed in the shape of surrounding the gate. The performance of the proposed device is analyzed through comparison with double gate thin intrinsic TFET (DGTI) TFET ...
International Technology Roadmap for Semiconductors. Process Integration, Devices, and Structures, http://www.itrs2.net
T. Uemura and T. Baba, "First demonstration of a planar- type surface tunnel transistor (S-I-T): lateral inter band tunnel device", Solid-State Electronics, Vol. 40, No. 1-8. pp. 519-522, 1996.
W. Y. Choi and W. Lee, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors", IEEE Trans. Electron Devices, Vol. 57, No. 9, pp. 2317-2319 Sep. 2010.
K. Boucart and A. M. Ionescu, "Double-Gate Tunnel FET With High- ${\kappa}$ Gate Dielectric", IEEE Trans. Electron Devices, Vol. 54, No. 7, pp. 1725-1733, Jul. 2007.
A. S. Verhulst, W. G. Vandenberghe, K. Maex and G.Groeseneken, "Boosting the on-current of a nchannel nanowire tunnel field-effect transistor by source material optimization", J. Appl. Phys, Vol. 104, p. 064514, Jul. 2008.
W. Lee and W. Y. Choi, "Influence of Inversion Layer on Tunneling Field-Effect Transistors" IEEE Electron Device Lett, Vol. 32, No. 9, pp. 1191-1193, Sep. 2011.
C. Anghel, Hraziia, A. Gupta, A. Amara and A. Vladimirescu, "30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current" IEEE Trans. Electron Devices, Vol. 58, No. 6, pp. 1649-1654, Jun. 2011.
A. S. Verhulst, W. G. Vandenberghe, K. Maex and G. Groeseneken, "Tunnel field-effect transistor without gate-drain overlap", Appl. Phys. Lett, Vol. 91, p. 053102, Jun. 2007.
V. Nagavarapu, R. Jhaveri and J. C. S. Woo, "The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor", IEEE Trans. Electron Devices, Vol. 55, No. 4, pp. 1013-1019, Apr. 2008.
S. H. Kim, S. Agarwal, Z. A. Jacobson, P. Matheu, C. Hu and T.-J. K. Liu, "Tunnel Field Effect Transistor With Raised Germanium Source", IEEE Electron Device Lett. Vol. 31, No. 10, pp. 1107-1109, Oct. 2010.
R. Asra, K. V. R. M. Murali and V. R. Rao, "A Binary Tunnel Field Effect Transistor with a Steep Sub-threshold Swing and Increased ON Current", Jpn. J. Appl. Phys, Vol. 49, p. 120203, Dec. 2010.
M.-C. Sun, S. W. Kim, H. W. Kim, G. Kim, H. Kim, J.-H. Lee, H. Shin and B.-G. Park, "Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits", Jpn. J. Appl. Phys, Vol. 51, p. 04DC03, Apr. 2012.
O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions", IEEE Electron Device Lett, Vol. 29, No. 9, pp. 1074-1077, Sep. 2008.
K. K. Bhuwalka, S. Sedlmaier, A. K. Ludsteck, J. Schulze, and I. Eisele, "Vertical Tunnel Field- Effect Transistor", IEEE Trans. Electron Devices, Vol. 51, No. 2, pp. 279-282, Feb. 2004.
K. K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and I.Eisele, "P-Channel Tunnel Field-Effect Transistors down to Sub-50nm Channel Lengths", Jpn. J. Appl. Phys, Vol. 45, No. 4B, pp. 3106-3109, Apr. 2006.
P.-F. Wang, K. Hilsenbeck,T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, "Complementary tunneling transistor for low power application", Solid. State Electronics, Vol. 48, p. 2281-2286, Dec. 2004.
Z. X. Chen, H. Y. Yu, N. Singh, N. S. Shen, R. D. Sayanthan, G. Q. Lo,and D.-L. Kwong, "Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires", IEEE Electron Device Lett, Vol. 30, No. 7, pp. 754-756, Jul. 2009.
M. T. Bjork, J. Knoch, H. Schmid, H. Riel, and W. Riess, "Silicon nanowire tunneling field-effect transistors", Appl. Phys. Lett, Vol. 92, p. 193504, May. 2008.
K. Boucart and A. MIonescu, "Double-Gate Tunnel FET With High- ${\kappa}$ Gate Dielectric" IEEE Trans. Electron Devices, vol. 54, no. 7, Jul. 2007.
Ankur Beohar, Nandakishor Yadav and Santosh Kumar Vishvakarma, "Analysis of trap-assisted tunnelling in asymmetrical underlap 3D-cylindrical GAA-TFET based on hetero-spacer engineering for improved device reliability", IET Micro & Nano Lett, Vol. 12, Iss. 12, pp. 982-986, 2017.
S. W. Kim, W. Y. Choi, M.-C. Sun, H. W. Kim, and B.-G. Park, "Design Guideline of Si-Based LShaped Tunneling Field-Effect Transistors", Jpn. J. Appl. Phys, Vol. 51, p. 06FE09, Jun. 2012.
*원문 PDF 파일 및 링크정보가 존재하지 않을 경우 KISTI DDS 시스템에서 제공하는 원문복사서비스를 사용할 수 있습니다.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.