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NTIS 바로가기전기학회논문지 = The Transactions of the Korean Institute of Electrical Engineers, v.68 no.2, 2019년, pp.364 - 369
홍찬의 (School of Electronic and Display Engineering, Hoseo University) , 안진호 (School of Electronic and Display Engineering, Hoseo University)
Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed ...
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