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NTIS 바로가기마이크로전자 및 패키징 학회지 = Journal of the Microelectronics and Packaging Society, v.27 no.1, 2020년, pp.17 - 24
서한결 (서울과학기술대학교 나노IT디자인융합대학원) , 박해성 (서울과학기술대학교 일반대학원 기계공학과) , 김사라은경 (서울과학기술대학교 나노IT디자인융합대학원)
As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bond...
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핵심어 | 질문 | 논문에서 추출한 답변 |
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Cu-SiO2 하이브리드 본딩 공정이란? | Cu-SiO2 하이브리드 본딩 공정은 일반적으로 Fig. 3과같이 산화물 높이 저감 기술(oxide recess control method)과 구리 디싱 제어 기술(Cu dishing control method)로 설명할 수 있다. Fig. | |
본딩 공정의 종류는? | 본딩 공정의 종류에는 금속 대 금속(metal-to-metal) 본딩, 산화물 대 산화물(oxide-to-oxide) 본딩, 고분자 대 고분자(polymer-to-polymer) 본딩, 그리고 금속과 산화물 또는 금속과 고분자를 동시에 본딩하는 하이브리드(hybrid)본딩이 있다.1,2) 이 중 금속 대 금속 본딩이 열적 기계적 신뢰성이 좋을 뿐 아니라 전기적 특성도 매우 우수하여 소자 적층 시 매우 적합한 공정이다. | |
패시베이션(passivation)하는 방법의 장점 | 플라즈마 전처리 방법 중에는 구리 표면의 자연산화구리를 제거하고 구리 표면을 구리 질화물로 패시베이션(passivation)하는 방법이 있다.5,8,35) 구리 질화물 박막은 구리 표면의 산화를 방지하고 억제할 뿐 아니라 화학양론(stoichiometry)과 결정구조에 따라서 100~470°C 사이에서 분해된다고 보고되어 있고,36) 이에 200°C 이하의 저온 Cu-SiO2 하이브리드 본딩에 높은 적용 가능성을 보이고 있다. 또한, Cu3N 박막이나 Cu4N 박막은 전기전도도가 반도체 이상으로 높다는 장점도 있다. |
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