[논문]3D 패키징을 위한 Scallop-free TSV와 Cu Pillar 및 하이브리드 본딩

장예진; 정재필

doi:10.6117/kmeps.2022.29.4.001

3D 패키징을 위한 Scallop-free TSV와 Cu Pillar 및 하이브리드 본딩
Scallop-free TSV, Copper Pillar and Hybrid Bonding for 3D Packaging 원문보기

마이크로전자 및 패키징 학회지 = Journal of the Microelectronics and Packaging Society, v.29 no.4, 2022년, pp.1 - 8

장예진 (서울시립대학교 신소재공학과) , 정재필 (서울시립대학교 신소재공학과)

초록
AI-Helper

TSV 기술을 포함한 고밀도, 고집적 패키징 기술은 IoT, 6G/5G 통신, HPC (high-performance computing)등 여러 분야에서 중요한 기술로 여겨지고 있다. 2차원에서 고집적화를 달성하는 것은 물리적 한계에 도달하게 되었으며, 따라서 3D 패키징 기술을 위하여 다양한 연구들이 진행되고 있다. 본 고에서는 scallop의 형성 원인과 영향, 매끈한 측벽을 만들기 위한 scallop-free 에칭 기술, TSV 표면의 Cu bonding에 대해서 자세히 조사하였다. 이러한 기술들은 고품질 TSV 형성 및 3D 패키징 기술에 영향을 줄 것으로 예상한다.

Abstract ▼ AI-Helper

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO2 hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.

주제어

표/그림 (7)

14)" alt="Fig. 1. Si DRIE (deep reactive ion etching) method: "scallop-free" (non-Bosch etching).¹⁴⁾" onerror="this.src='/images/noimg.png'" class="objectfit" /> 그림 Fig. 1. Si DRIE (deep reactive ion etching) method: "scallop-free" (non-Bosch etching).¹⁴⁾
그림 Fig. 2. Cu TSV made by "cycled etching" and "scallop-free etching"; (a) side wall with scallops; (b) scallop-free side wall.
그림 Fig. 3. Structure of chip connection (C2) bump
그림 Fig. 4. Cu pillar bonding at 170℃ with the nano-grained Sn-Ag solder of 5 μm total thickness; (a) before bonding with Sn- Ag solder cap; (b) after bonding (provided by Duksan Himetal Co. Ltd.).
그림 Fig. 5. Thin Sn-Cu solder layer having nano-meter sized grains electro-plated on a Cu substrate.
그림 Fig. 6. Low temperature TLP bonding between Cu substrate and Si chip using Sn-Ni nano-grained plating layer (bonded at 250℃ for 30 sec. under 0.1 MPa pressure).
그림 Fig. 7. Schematic of the ideal Cu-SiO₂ hybrid bonding; before contact (a), start bonding by annealing (b) and after bonding by annealing (c).

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저자의 다른 논문 :

표제어: PCR

동의어: Packet Collision Rate

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