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NTIS 바로가기전기전자학회논문지 = Journal of IKEEE, v.25 no.2, 2021년, pp.376 - 380
정장한 (Dept. of Electronics Engineering, Dankook University) , 도경일 (Dept. of Electronics Engineering, Dankook University) , 진승후 (Dept. of Electronics Engineering, Dankook University) , 고경진 (Dept. of Electronics Engineering, Dankook University) , 구용서 (Dept. of Electronics Engineering, Dankook University)
In this paper, we propose a novel ESD protection device with Latch-up immunity properties due to high holding voltages by improving the structure of a typical SCR. To verify the characteristics of the proposed ESD circuit, simulations were conducted using Synopsys TCAD and presented compared to exis...
Albert Z. H. Wang, "On-Chip ESD Protection for Integrated Circuits 2nd ed," Springer, 2002.
M. D. Ker and C. C. Yen, "Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latch up-Like Failure During System-Level ESD Test," IEEE J.Solid-State Circuits, vol.43, no.11, pp.2533-2545. 2008. DOI: 10.1109/JSSC.2008.2005451
O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, "ESD protection for high-voltage CMOS technologies," in Proc. EOS/ESD Symp., pp.77-86. 2006.
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