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NTIS 바로가기IEEE electron device letters : a publication of the IEEE Electron Devices Society, v.29 no.1, 2008년, pp.128 - 130
Sachid, A.B. (Indian Inst. of Technol. Bombay, Mumbai) , Manoj, C.R. (Indian Inst. of Technol. Bombay, Mumbai) , Sharma, D.K. (Indian Inst. of Technol. Bombay, Mumbai) , Rao, V.R. (Indian Inst. of Technol. Bombay, Mumbai)
The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs wi...
Kedzierski, J., Ieong, Meikei, Nowak, E., Kanarsky, T.S., Zhang, Ying, Roy, R., Boyd, D., Fried, D., Wong, H.-S.P.. Extension and source/drain design for high-performance FinFET devices. IEEE transactions on electron devices, vol.50, no.4, 952-958.
Trivedi, V.P., Fossum, J.G., Chowdhury, M.M.. Nanoscale FinFETs With Gate-Source/Drain Underlap. IEEE transactions on electron devices, vol.52, no.1, 56-62.
Chen, Qiang, Wang, Lihui, Meindl, James D.. Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs. Solid-state electronics, vol.49, no.2, 271-274.
International Technology Roadmap for Semiconductors 2005
Tsui, Bing-Yue, Chin, Li-Feng. A comprehensive study on the FIBL of nanoscale MOSFETs. IEEE transactions on electron devices, vol.51, no.10, 1733-1736.
Manoj, C. R., Rao, V. Ramgopal.
Impact of High-
Yeap, G.C.-F., Krishnan, S., Lin, Ming-Ren. Fringing-induced barrier lowering (FIBL) in sub-100 nm MOSFETs with high-K gate dielectrics. Electronics letters, vol.34, no.11, 1150-1152.
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Huang, Xuejue, Lee, Wen-Chin, Kuo, C., Hisamoto, D., Chang, Leland, Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Yang-Kyu, Asano, K., Subramanian, V., King, Tsu-Jae, Bokor, J., Hu, Chenming. Sub-50 nm P-channel FinFET. IEEE transactions on electron devices, vol.48, no.5, 880-886.
Mohapatra, N.R., Desai, M.P., Narendra, S.G., Rao, V.R.. The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance. IEEE transactions on electron devices, vol.49, no.5, 826-831.
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