[논문]EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory

Shin, Ho Hyun; Park, Young Min; Choi, Duheon; Kim, Byoung Jin; Cho, Dae-Hyung; Chung, Eui-Young

doi:10.1109/TC.2017.2723392

EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory

IEEE transactions on computers, v.67 no.1, 2018년, pp.32 - 44

Shin, Ho Hyun (Samsung Electronics Company, Ltd., Hwasung, Korea) , Park, Young Min (School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea) , Choi, Duheon (School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea) , Kim, Byoung Jin (School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea) , Cho, Dae-Hyung (School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea) , Chung, Eui-Young (School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea)

Abstract ▼ AI-Helper

For future exascale computing systems, ultra-high-density memories would be required that consume low power to process massive data. Of the various memory devices, 3D-stacked DRAMs using TSVs are a perfect solution for this purposes. In addition to providing high capacity, these provide functional flexibility to the computing system by attaching a logic die in each 3D-stacked DRAM chip. However, the high capacity 3D-stacked DRAMs suffer from a significant loss of refresh power, which is solely required to maintain data. Although various schemes have been proposed to mitigate this issue, they cannot be adopted by commercial products due to compatibility issues. To tackle this issue, we propose EXTREME, which effectively reduces the refresh power of 3D-Stacked DRAMs. In order to retain the compatibility with OS, a simple page table manager is implemented at the logic die of 3D-stacked DRAM devices, which pins the page table to a specific memory space. The experiment results demonstrate that this reduces the refresh power at idle time by up to 98 percent with 16 KB of SRAM (static RAM) and 64 KB of DRAM register overhead for a 2 GB 3D-stacked DRAM device.

참고문헌 (23)

10.1109/MICRO.2007.13
10.1145/280756.280792
10.1109/HPCA.2006.1598122
10.1145/1950365.1950391
Baek, Seungjae, Sangyeun Cho, Melhem, Rami. Refresh Now and Then. IEEE transactions on computers, vol.63, no.12, 3114-3126.

상세보기
10.1145/1669112.1669156
Low-power function of mobile RAM-partial array self refresh (PASR) 2005
Proc 40th Annu Int Symp Comput Archit An experimental study of data retention behavior in modern DRAM devices: Implications for retention time profiling mechanisms liu 2013 60
Kinam Kim, Jooyoung Lee. A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.30, no.8, 846-848.

상세보기
CACTI 6.0: A tool to model large caches laboratories 2009
Hybrid memory cube specification 2.0 2014
JESD235: High bandwidth memory (HBM) DRAM 2013
DDR3 SDRAM datasheet 2006
Sohn, Kyomin, Yun, Won-Joo, Oh, Reum, Oh, Chi-Sung, Seo, Seong-Young, Park, Min-Sang, Shin, Dong-Hak, Jung, Won-Chang, Shin, Sang-Hoon, Ryu, Je-Min, Yu, Hye-Seung, Jung, Jae-Hun, Lee, Hyunui, Kang, Seok-Yong, Sohn, Young-Soo, Choi, Jung-Hwan, Bae, Yong-Cheol, Jang, Seong-Jin, Jin, Gyoyoung. A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution. IEEE journal of solid-state circuits, vol.52, no.1, 250-260.

상세보기
ARM System Developer's Guide Designing and Optimizing System Software sloss 2004
DDR4 SDRAM datasheet 2014
Liu, Jamie, Jaiyen, Ben, Veras, Richard, Mutlu, Onur. RAIDR : Retention-Aware Intelligent DRAM Refresh. Computer architecture news, vol.40, no.3, 1-12.

상세보기
10.1007/978-1-4419-7124-1
Operating System Concepts silberschatz 2010
Calculating memory system power for DDR3 2007
Rosenfeld, P, Cooper-Balis, E, Jacob, B. DRAMSim2: A Cycle Accurate Memory System Simulator. IEEE computer architecture letters, vol.10, no.1, 16-19.

상세보기
SIGARCH Comput Archit News The Gem5 simulator binkert 2011 10.1145/2024716.2024718 39 1

상세보기
10.1145/1454115.1454128

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EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory

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EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory

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