IPC분류정보
국가/구분 |
United States(US) Patent
공개
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0623243
(2009-11-20)
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공개번호 |
US-0136793
(2010-06-03)
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발명자
/ 주소 |
- Chen, Zhigang
- Rauf, Shahid
- Merry, Walter R.
- Dorf, Leonid
- Ramaswamy, Kartik
- Collins, Kenneth S.
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출원인 / 주소 |
|
대리인 / 주소 |
PATTERSON & SHERIDAN, LLP - - APPM/TX
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인용정보 |
피인용 횟수 :
0 인용 특허 :
0 |
초록
▼
In a plasma reactor having an electrostatic chuck, wafer voltage may be determined from RF measurements at the bias input using previously determined constants based upon transmission line properties of the bias input, and this wafer voltage may be used to accurately control the DC wafer clamping vo
In a plasma reactor having an electrostatic chuck, wafer voltage may be determined from RF measurements at the bias input using previously determined constants based upon transmission line properties of the bias input, and this wafer voltage may be used to accurately control the DC wafer clamping voltage.
대표청구항
▼
1. A plasma reactor, comprising: a wafer support; a radio frequency (RF) match network coupled to the wafer support; a first RF power source coupled to the RF match network and capable of operating at a first frequency; a second RF power source coupled to the RF match network and capable of operati
1. A plasma reactor, comprising: a wafer support; a radio frequency (RF) match network coupled to the wafer support; a first RF power source coupled to the RF match network and capable of operating at a first frequency; a second RF power source coupled to the RF match network and capable of operating at a second frequency different than the first frequency; a direct current (DC) power source coupled to the wafer support; a measurement instrument coupled to the RF match network for measuring a voltage at the match network attributable to each of the first frequency and the second frequency; and a controller capable of calculating a wafer voltage signal as a function of the measured voltage and for calculating a DC voltage at a wafer on the wafer support, the controller also capable of adjusting DC power applied to the wafer support from the DC power source in response to the calculated wafer voltage signal. 2. The reactor of claim 1, further comprising a third RF power source coupled to a gas distribution showerhead of the plasma reactor. 3. The reactor of claim 2, further comprising a coolant source coupled with the wafer support. 4. The reactor of claim 3, further comprising an isolation capacitor coupled between the RF match network and the wafer support. 5. The reactor of claim 1, wherein the plasma reactor has a gas distribution showerhead that is grounded. 6. The reactor of claim 5, further comprising a coolant source coupled with the wafer support. 7. The reactor of claim 6, further comprising an isolation capacitor coupled between the RF match network and the wafer support. 8. A method of processing a wafer while controlling an electrostatic chuck clamping voltage, comprising: applying a first RF current to the electrostatic chuck through an RF match network at a first frequency from a first RF power source; applying a second RF current to the electrostatic chuck through the RF match network at a second frequency from a second RF power source; applying DC voltage to the electrostatic chuck; measuring a third RF current at the match network attributable to the first frequency; measuring a fourth RF current at the match network attributable to the second frequency; calculating a wafer voltage at the first and second frequencies based upon the measured third and fourth currents; calculating a DC component of the wafer voltage attributed to each frequency; calculating a total DC voltage at the wafer based upon the DC component attributable to each frequency and a DC component attributable to an intermodulation of the first and second frequency; and adjusting the applied DC voltage to maintain a predetermined difference between the applied DC voltage and the total DC voltage at the wafer. 9. The method of claim 8, further comprising flowing a cooling fluid through the electrostatic chuck. 10. The method of claim 8, further comprising etching the wafer. 11. The method of claim 8, wherein the wafer is disposed in a plasma reactor having a grounded gas distribution showerhead. 12. The method of claim 11, further comprising flowing a cooling fluid through the electrostatic chuck. 13. The method of claim 11, wherein the total DC voltage at the wafer is calculated using the equation: V D C = - 3 4 * ( A g A p ) 2 - 1 ( A g A p ) 2 + 1 [ V RF ( f 1 ) + V RF ( f 2 ) - 2 3 V RF ( f 1 ) * V RF ( f 2 ) V RF ( f 1 ) + V RF ( f 2 ) ] , where Ag represents an area of the gas distribution showerhead, Ap represents an area of the electrostatic chuck, VDC(f1) represents the DC component of the wafer voltage attributed to the first frequency, and VDC(f2) represents the DC component of the wafer voltage attributed to the second frequency. 14. The method of claim 13, further comprising flowing a cooling fluid through the electrostatic chuck. 15. The method of claim 13, further comprising etching the wafer. 16. A method of processing a wafer while controlling an electrostatic chuck clamping voltage in a plasma reactor, comprising: applying a first RF current to the electrostatic chuck through an RF match network at a first frequency from a first RF power source; applying a second RF current to the electrostatic chuck through the RF match network at a second frequency from a second RF power source; applying DC voltage to electrostatic chuck; applying a third RF current to a gas distribution showerhead of the plasma reactor at a third frequency from a third RF power source; measuring a fourth RF current at the match network attributable to the first frequency; measuring a fifth RF current at the match network attributable to the second frequency; calculating a wafer voltage at the third frequency based upon the third current, the fourth current and the fifth current; calculating the DC component of the wafer voltage attributed to the first frequency, the second frequency, and the third frequency; calculating the total DC voltage at the wafer based upon the DC component attributable to each frequency; adjusting the applied DC voltage to maintain a predetermined difference between the applied DC voltage and the total DC voltage at the wafer. 17. The method of claim 16, further comprising flowing a cooling fluid through the electrostatic chuck. 18. The method of claim 16, further comprising etching the wafer. 19. The method of claim 16, wherein the total DC voltage is calculated using the following equation: V D C = - 3 4 * F 1 * F 2 - 1 F 2 + 1 * [ V D C ( f 1 ) + V D C ( f 2 ) + V D C ( f 3 ) - ( 2 3 * F 3 * V D C ( f 1 ) * V D C ( f 2 ) + F 4 * V D C ( f 1 ) * V D C ( f 3 ) + F 5 * V D C ( f 2 ) * V D C ( f 3 ) V D C ( f 1 ) + V D C ( f 2 ) + V D C ( f 3 ) ) ] , wherein F 1 = 1.2 - 3.3 * p 2 , F 2 = ( A g A p ) 4 - 0.2 * p 3 , F 3 = ( P ( f 1 ) * P ( f 2 ) P ( f 1 ) + P ( f 2 ) ) 0.06 , F 4 = ( P ( f 1 ) ) 0.39 , and F 5 = ( P ( f 2 ) ) 0.22 , where p is a measured pressure of the plasma reactor, P(f1) is the power from the first RF power source measured at the RF match network, P(f2) is the power from the second RF power source measured at the RF match network, Ag represents an area of the gas distribution showerhead, Ap represents an area of the electrostatic chuck, VDC(f1) represents the DC component of the wafer voltage attributed to the first frequency, VDC(f2) represents the DC component of the wafer voltage attributed to the second frequency, and VDC(f3) represents the DC component of the wafer voltage attributed to the third frequency. 20. The method of claim 19 further comprising flowing a cooling fluid through the electrostatic chuck.
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