INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, MAIN PROCESSOR CORE, PROGRAM, INFORMATION PROCESSING METHOD, AND SUB PROCESSOR CORE
원문보기
IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
G06F-013/16
G06F-009/50
G06F-009/54
G06F-003/06
출원번호
US-0552179
(2015-12-28)
공개번호
US-0074980
(2018-03-15)
우선권정보
JP-2015-030566 (2015-02-19)
국제출원번호
PCT/JP2015/006491
(2015-12-28)
발명자
/ 주소
KAWAHARA, Aoi
출원인 / 주소
KAWAHARA, Aoi
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
A main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core are included. An operating system is incorporated in the main processor core, and no operating system is incorporated in the sub processor core. Shared memories are f
A main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core are included. An operating system is incorporated in the main processor core, and no operating system is incorporated in the sub processor core. Shared memories are formed in the first and second memories, respectively. Data in the shared memories of the first and second memories are synchronized. The main processor core is configured to synchronize the data in the shared memories formed in the first and second memories while the sub processor core stops operating.
대표청구항▼
1. An information processing device comprising a main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core, an operating system being incorporated in the main processor core, no operating system being incorporated in the sub p
1. An information processing device comprising a main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core, an operating system being incorporated in the main processor core, no operating system being incorporated in the sub processor core, wherein: a shared memory area is formed in the first memory, a shared memory area is formed in the second memory, and data in the shared memory areas of the first and second memories are synchronized; andthe main processor core is configured to synchronize the data in the shared memory areas formed in the first and second memories while the sub processor core stops operating. 2. The information processing device according to claim 1, wherein: the sub processor core is configured to request the main processor core to execute predetermined information processing, and also stop operating; andthe main processor core is configured to, after executing the predetermined information processing requested by the sub processor core, copy data updated through the predetermined information processing in one of the shared memory areas into the other of the shared memory areas and then execute control to restart operation of the sub processor core. 3. The information processing device according to claim 1, wherein: the sub processor core is configured to request the main processor core to execute information processing, and also stop operating, the information processing being updating data in the shared memory area formed in the second memory; andthe main processor core is configured to, after executing the information processing requested by the sub processor core, copy the data in the shared memory area formed in the second memory updated through the information processing into the shared memory area formed in the first memory and then execute control to restart operation of the sub processor core, the information processing being updating the data in the shared memory area formed in the second memory. 4. The information processing device according to claim 2, wherein the information processing is a system call. 5. The information processing device according to claim 1, wherein the main processor core is configured to, when the sub processor core stops operating, check whether or not data in the shared memory area formed in the second memory has been updated and copy the updated data in the shared memory area formed in the second memory into the shared memory area formed in the first memory. 6. The information processing device according to claim 1, wherein the main processor core is configured to, when the sub processor core stops operating, copy updated data in the shared memory area formed in the first memory into the shared memory area formed in the second memory. 7. The information processing device according to claim 1, wherein: the sub processor core is configured to request the main processor core to form a shared memory area, and also stop operating; andthe main processor core is configured to, in response to a request by the sub processor core, form the shared memory areas in the first and second memories and then execute control to restart operation of the sub processor core. 8. An information processing method executed by an information processing device comprising a main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core, an operating system being incorporated in the main processor core, no operating system being incorporated in the sub processor core, shared memory areas being formed in the first and second memories, respectively, data in the shared memory areas of the first and second memories being synchronized, the information processing method comprising: by the main processor core, synchronizing the data in the shared memory areas formed in the first and second memories while the sub processor core stops operating. 9. The information processing method according to claim 8, comprising: by the sub processor core, requesting the main processor core to execute predetermined information processing, and also stopping operating; andby the main processor core, after executing the predetermined information processing requested by the sub processor core, copying data updated through the predetermined information processing in one of the shared memory areas into the other of the shared memory areas and then executing control to restart operation of the sub processor core. 10. A main processor core in which an operating system is incorporated, the main processor core having a function to control a sub processor core in which no operating system is incorporated, wherein: a first memory is included;a shared memory area is formed in the first memory, data in the shared memory area is synchronized with data in a second memory included by the sub processor core; anda shared memory synchronization unit is included, the shared memory synchronization unit being configured to synchronize the data in the shared memory area formed in the first memory with data in a shared memory area formed in the second memory while the sub processor core stops operating. 11-13. (canceled)
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