Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending
Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending through the substrate assembly provide the transistor source and ground voltages, and horizontal electrically conductive access lines at multiple device levels provide the transistor gate voltages. Process flows for fabricating the 3D DRAM arrays are also described.
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1. A three-dimensional DRAM array, comprising: a substrate assembly comprising multiple device-tiers vertically separated from one another by dielectric separation levels, each of the device tiers comprising a dielectric device level and at least one conductive device level vertically adjacent the d
1. A three-dimensional DRAM array, comprising: a substrate assembly comprising multiple device-tiers vertically separated from one another by dielectric separation levels, each of the device tiers comprising a dielectric device level and at least one conductive device level vertically adjacent the dielectric device level;electrically conductive data-line pillars vertically extending through at least a portion of the device tiers and the dielectric separation levels, the data-line pillars spaced along multiple first rows;electrically conductive ground pillars vertically extending through at least a portion of the device tiers and the dielectric separation levels, the ground pillars spaced along multiple second rows, the first and second rows both extending in a first horizontal direction and alternating with one another in a second horizontal direction; andmemory cells formed within the device tiers, each of the memory cells at least partially surrounding a respective one of the conductive data-line pillars and comprising a transistor and a capacitor electrically connected between that data-line pillar and one or more of the ground pillars,wherein the memory cells comprise rows of memory cells extending in the first horizontal direction, and wherein transistors of the memory cells within each row and within a tier share a common access line. 2. The DRAM array of claim 1, wherein each of the memory cells comprises a transistor channel and a capacitor node plate both formed within a cavity within the dielectric device level of the respective device tier and at least one transistor gate formed within at least one cavity within the at least one conductive device level of the respective device tier. 3. The DRAM array of claim 2, wherein the transistor channel of each cell comprises a semiconductor ring at least partially surrounding the respective conductive data-line pillar, and wherein the capacitor node plate of each cell comprises an electrically conductive ring at least partially surrounding the respective semiconductor ring, the semiconductor ring and the electrically conductive ring both being electrically insulated from the at least one conductive device level. 4. The DRAM array of claim 3, wherein each transistor gate comprises an electrically conductive ring surrounding and electrically insulated from the conductive data-line pillars and electrically insulated from the semiconductor rings and the ground pillars. 5. The DRAM array of claim 2, wherein a capacitor area for each of the memory cells is defined by an area of horizontal overlap between the respective node plate and a portion of the at least one conductive device level surrounding the at least one cavity in which the at least one transistor gate is formed. 6. The DRAM array of claim 2, wherein the node plates are made of doped polysilicon. 7. The DRAM array of claim 2, wherein the cavities formed within the dielectric device levels and the conductive device levels are each lined with a material having a dielectric constant greater than 3.6. 8. The DRAM array of claim 1, wherein each device tier comprises the dielectric device level sandwiched between two conductive device levels, and wherein the memory cells comprise double gates. 9. The DRAM array of claim 1, wherein each device tier comprises only one conductive device levels adjacent the dielectric device level, and wherein the memory cells comprise single gates. 10. The DRAM array of claim 1, further comprising multiple vertical dummy pillars arranged along the first rows alternatingly with the conductive data-line pillars and multiple conductive rings surrounding the dummy pillars to form respective portions of the access lines. 11. The DRAM array of claim 1, wherein the conductive device levels, the ground pillars, and the data-line pillars comprise doped polysilicon. 12. The DRAM array of claim 1, wherein the dielectric device levels comprise silicon oxycarbide and the isolation levels comprise silicon nitride. 13. The DRAM array of claim 1, wherein the access lines comprise titanium nitride and tungsten. 14. A memory cell formed within a substrate comprising a dielectric device level and at least one electrically conductive device level vertically adjacent the dielectric device level, the memory cell comprising: a transistor comprising, a semiconductor ring formed within a dielectric device level in electrical contact with a first conductive pillar extending vertically through the dielectric and conductive device levels, the first conductive pillar connected to a source node, andat least one electrically conductive ring forming at least one respective transistor gate within the at least one electrically conductive device level surrounding the first conductive pillar, the transistor gate being electrically insulated from the first conductive pillar and the semiconductor ring and being connected to a gate voltage; anda capacitor comprising a conductive ring forming a capacitor node plate within the dielectric device level at least partially surrounding and in electrical contact with the semiconductor ring, the capacitor node plate being electrically insulated from a second conductive pillar extending through the dielectric and conductive device levels, the second conductive pillar connected to a ground node, anda ground plate formed by portions of the conductive device level electrically connected to the second conductive pillar and horizontally overlapping with the capacitor node plate. 15. The memory cell of claim 14, wherein the dielectric device level is disposed between two adjacent conductive device levels, and wherein the transistor is double-gated by the two respective electrically conductive rings formed with in the conductive device levels. 16. The memory cell of claim 14, wherein the at least one transistor gate is made of titanium nitride and tungsten. 17. A method of forming a DRAM array, comprising: forming multiple device-tiers over a substrate, the multiple device tiers vertically separated from one another by dielectric separation levels, each of the device tiers comprising a dielectric device level and at least one conductive device level;forming electrically conductive data-line pillars vertically extending through at least a portion of the device tiers and the dielectric separation levels, the data-line pillars spaced along multiple first rows;forming electrically conductive ground pillars vertically extending through at least a portion of the device tiers and the dielectric separation levels, the ground pillars spaced along multiple second rows, the first and second rows both extending in a first horizontal direction and alternating with one another in a second horizontal direction; andforming memory cells within the device tiers, the memory cells at least partially surrounding a respective one of the conductive data-line pillars, and comprising a transistor and a capacitor coupled between a data-line pillar and one or more of the ground pillars,wherein the memory cells comprise rows of memory cells extending in the first horizontal direction, and wherein transistors of the memory cells within each row and within a conductive device level share a common access line. 18. The method of claim 17, wherein forming the memory cells comprises: forming a transistor channel and a capacitor node plate within a cavity within the dielectric device level of a respective device tier; andforming at least one transistor gate formed within at least one cavity within the at least one conductive device level of the respective device tier. 19. The method of claim 18, wherein forming the memory cells comprises: forming a semiconductor ring formed within a dielectric device level in electrical contact with a first conductive pillar extending vertically through the dielectric and conductive device levels, the first conductive pillar connected to a source node, andforming at least one electrically conductive ring forming at least one respective transistor gate within the at least one electrically conductive device level surrounding the first conductive pillar, the transistor gate being electrically insulated from the first conductive pillar and the semiconductor ring and being connected to a gate voltage; andforming a capacitor comprising, forming a conductive ring forming a capacitor node plate within the dielectric device level at least partially surrounding and in electrical contact with the semiconductor ring, the capacitor node plate being electrically insulated from a second conductive pillar extending through the dielectric and conductive device levels, the second conductive pillar connected to a ground node, andforming a ground plate in portions of the conductive device level electrically connected to the second conductive pillar and horizontally overlapping with the capacitor node plate. 20. The method of claim 18, wherein forming the transistor channel of each cell comprises: forming a semiconductor ring at least partially surrounding the respective conductive data-line pillar, andforming a capacitor node plate comprising an electrically conductive ring at least partially surrounding the respective semiconductor ring, the semiconductor ring and the electrically conductive ring both being electrically insulated from the at least one conductive device level. 21. The method of claim 20, wherein a capacitor area for each of the memory cells is defined by an area of horizontal overlap between the respective node plate and a portion of the at least one conductive device level surrounding the at least one cavity in which the at least one transistor gate is formed. 22. The method of claim 21, wherein each device tier comprises the dielectric device level sandwiched between two conductive device levels, and wherein forming the memory cells comprises forming double gates of the transistors. 23. The method of claim 17, wherein each device tier comprises only one conductive device level adjacent the dielectric device level, and wherein the memory cells comprise single gates. 24. The method of claim 17, further comprising; forming multiple vertical dummy pillars arranged along the first rows alternatingly with the conductive data-line pillars; andforming multiple conductive rings surrounding the dummy pillars to form respective portions of the access lines.
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