METHOD FOR PASSIVATING FULL FRONT-SIDE DEEP TRENCH ISOLATION STRUCTURE
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IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
H01L-027/146
H01L-021/762
H01L-021/285
H01L-021/02
출원번호
16725687
(2019-12-23)
공개번호
20210193704
(2021-06-24)
발명자
/ 주소
Sun, Shiyu
출원인 / 주소
Sun, Shiyu
인용정보
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0인용 특허 :
0
초록▼
A method for forming a deep trench isolation structure for a CMOS image sensor includes providing a trench that extends from a first side toward a second side of a semiconductor substrate. The trench has an opening on the first side and a bottom and sides. A conformal layer of B-doped oxide is depos
A method for forming a deep trench isolation structure for a CMOS image sensor includes providing a trench that extends from a first side toward a second side of a semiconductor substrate. The trench has an opening on the first side and a bottom and sides. A conformal layer of B-doped oxide is deposited on the bottom and sides of the trench and is less than half a width of the trench leaving a depthwise recess in the trench. A second material is deposited on the conformal layer of B-doped oxide in the trench filling the recess in the trench to the first side. The conformal layer of B-doped oxide is annealed driving boron from the conformal layer of B-doped oxide to the semiconductor substrate forming a B-doped region as a passivation layer juxtaposed next to the conformal layer of B-doped oxide having negative fixed charges.
대표청구항▼
1. A method for forming a deep trench isolation structure for a CMOS image sensor, comprising: providing a semiconductor substrate having a trench, wherein the trench extends from a first side of the semiconductor substrate toward a second side of the semiconductor substrate, wherein the trench has
1. A method for forming a deep trench isolation structure for a CMOS image sensor, comprising: providing a semiconductor substrate having a trench, wherein the trench extends from a first side of the semiconductor substrate toward a second side of the semiconductor substrate, wherein the trench has an opening on the first side and a bottom and sides of the trench are formed of the semiconductor substrate;depositing a conformal layer of boron (B)-doped oxide at least on the bottom and sides of the trench, wherein the conformal layer of B-doped oxide is less than half a width of the trench to leave a depthwise recess in the trench;depositing a second material at least on the conformal layer of B-doped oxide in the trench, wherein the second material fills the recess in the trench to at least the first side; andannealing the conformal layer of B-doped oxide to drive boron from the conformal layer of B-doped oxide to the semiconductor substrate that forms a B-doped region as a passivation layer juxtaposed next to the conformal layer of B-doped oxide, and the conformal layer of B-doped oxide having negative fixed charges. 2. The method of claim 1, wherein said depositing the conformal layer of B-doped oxide includes atomic layer deposition or chemical vapor deposition at a deposition temperature between 300° C. and 500° C. 3. The method of claim 1, wherein said depositing the second material includes depositing doped polysilicon by chemical vapor deposition at a deposition temperature between 450° C. to 550° C. 4. The method of claim 1, wherein the conformal layer of B-doped oxide is selected from a borosilicate glass and B-doped dielectrics. 5. The method of claim 1, wherein the second material comprises doped polysilicon. 6. The method of claim 1, wherein the second material comprises a dielectric material. 7. The method of claim 1, wherein the conformal layer of B-doped oxide is 10 nm to 30 nm thick. 8. The method of claim 1, wherein the deposited conformal layer of B-doped oxide has a boron atomic concentration of 5% to 20% before annealing. 9. The method of claim 1, wherein the second material comprises doped polysilicon and the annealing of the conformal layer of B-doped oxide further electrically activates the doped polysilicon. 10. The method of claim 1, wherein the second material comprises doped polysilicon, wherein the annealing of the conformal layer of B-doped oxide occurs before depositing the doped polysilicon, and wherein a second annealing is performed after said depositing the doped polysilicon to electrically activate the doped polysilicon. 11. The method of claim 1, wherein the second material is blanket deposited, and wherein the method further comprises chemical mechanical polishing the second material to the semiconductor substrate. 12. The method of claim 1, wherein the annealing of the conformal layer of B-doped oxide is conducted from 800° C. to 1000° C. and for a time of 1 min to 60 min in an inert ambient atmosphere at a pressure of 0.1 Torr to 760 Torr. 13. The method of claim 1, wherein annealing of the conformal layer of B-doped oxide occurs prior to a formation of a photodiode in the semiconductor substrate. 14. The method of claim 1, further comprising: forming a photodiode proximate the first side of the semiconductor substrate proximate to the deep trench isolation structure after the annealing of the conformal layer of B-doped oxide; andthinning the second side of the semiconductor substrate to a level of the passivation layer at the bottom of the trench to form a full deep trench isolation structure extending from the first side to the second side of the semiconductor substrate. 15. The method of claim 14, further comprising: forming an interlayer dielectric layer on the first side of the semiconductor substrate including metal conductors and vias disposed in the interlayer dielectric layer;forming a buffer oxide layer on the second side of the semiconductor substrate;forming a metal grid on the buffer oxide layer;forming a color filter on the buffer oxide layer;and forming a microlens on the color filter. 16. The method of claim 15, further comprising bonding the interlayer dielectric layer to an application-specific integrated circuit (ASIC) wafer. 17. The method of claim 14, further comprising forming at least a pixel transistor proximate to the first side above the photodiode, the pixel transistor having a gate electrode formed on a surface of the first side. 18. A semiconductor structure for a CMOS image sensor, comprising: a semiconductor substrate having a first side and a second side; anda deep trench isolation structure extending from the first side toward the second side of the semiconductor substrate, wherein the deep trench isolation structure includes: a trench having a bottom and sides formed of the semiconductor substrate;a boron (B)-doped oxide layer on the bottom and sides of the trench; anda second material filling the trench at least to the first side of the semiconductor substrate, wherein boron is present in regions of the semiconductor substrate on the bottom and sides of the trench as a passivation layer, wherein the B-doped oxide layer has negative fixed charges forming a hole accumulation layer around the trench, and wherein the second material is juxtaposed next to the B-doped oxide layer and extends depthwise in the center of the trench. 19. The semiconductor structure of claim 18, wherein the B-doped oxide layer is selected from borosilicate glass and B-doped dielectrics. 20. The semiconductor structure of claim 18, wherein the second material comprises doped polysilicon. 21. The semiconductor structure of claim 18, wherein the second material comprises a dielectric material. 22. The semiconductor structure of claim 18, wherein the B-doped oxide layer is 3 nm to 30 nm thick. 23. The semiconductor structure of claim 18, wherein the B-doped oxide layer has a boron atomic concentration of 5% to 20% as deposited. 24. The semiconductor structure of claim 18, further comprising a photodiode proximate the first side of the semiconductor substrate and proximate to the deep trench isolation structure. 25. The semiconductor structure of claim 24, further comprising at least a pixel transistor, disposed proximate to the first side above the photodiode, the pixel transistor having a gate electrode formed on a surface of the first side. 26. The semiconductor structure of claim 25, further comprising an interlayer dielectric layer on the first side of the semiconductor substrate including metal conductors and vias disposed in the interlayer dielectric layer. 27. The semiconductor structure of claim 26, wherein the deep trench isolation structure extends from the first side to the second side of the semiconductor substrate. 28. The semiconductor structure of claim 27, further comprising: a buffer oxide layer disposed on the second side of the semiconductor substrate and on the passivation layer at the bottom of the deep trench isolation structure;a metal grid disposed on the buffer oxide layer;a color filter disposed on the buffer oxide layer;a microlens disposed on the color filter; andan application-specific integrated circuit (ASIC) wafer bonded to the interlayer dielectric layer. 29. The semiconductor structure of claim 18, wherein the deep trench isolation structure is a grid of intersecting deep trench isolation structures that encloses a plurality of photodiode within the intersecting deep trench isolation structures and electrically isolating individual photodiodes from adjacent photodiodes.
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