초록 ▼

A programmable logic array having a number of inputs for receiving operand data and a number of outputs for furnishing the results of Boolean operations upon the operand data is provided with a precharge signal generator responsive to a state transition in the operand data for generating a precharge

A programmable logic array having a number of inputs for receiving operand data and a number of outputs for furnishing the results of Boolean operations upon the operand data is provided with a precharge signal generator responsive to a state transition in the operand data for generating a precharge signal. The buffered operand data is furnished to an AND plane, and pullup circuits associated therewith are responsive to the precharge signal for charging the AND plane and sustaining the charge on all AND plane array lines in the logical ONE state. An OR plane is connected to the outputs of the AND plane, and pullup transistors associated with the OR plane and responsive to the precharge signal for charging the OR plane and sustaining the charge on all OR plane array lines in the logical ONE state. The PLA outputs are taken from the buffered outputs of the OR plane.

대표청구항 ▼

A programmable logic array for performing Boolean operations upon operand data, comprising: a precharge signal generator responsive to new operand data for generating a precharge signal; an AND plane, said operand data being applied thereto; a plurality of pullup circuits associated with said AND pl

A programmable logic array for performing Boolean operations upon operand data, comprising: a precharge signal generator responsive to new operand data for generating a precharge signal; an AND plane, said operand data being applied thereto; a plurality of pullup circuits associated with said AND plane and responsive to the output of said precharge signal generator for charging said AND plane in response to said precharge signal and sustaining charge in said AND plane; an OR plane connected to the outputs of said AND plane; and a plurality of pullup transistors associated with said OR plane and responsive to the output of said precharge signal generator for charging said OR plane in response to said precharge signal and sustaining charge in said OR plane.