[특허]Polysilicon linewidth reduction using a BARC-poly etch process

[미국특허] Polysilicon linewidth reduction using a BARC-poly etch process 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G03F-007/00
출원번호	US-0865358 (1997-05-29)
발명자 / 주소	Rogers Daty Michael Thaker Guatam V.
출원인 / 주소	Texas Instruments Incorporated
대리인 / 주소	Garner
인용정보	피인용 횟수 : 26 인용 특허 : 9

초록 ▼

A process for forming a polysilicon line having linewidths below 0.35 .mu.m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., I-line lithography). The resist pattern (40) has minimum dimensions of 0.30 .mu.m or greater. The BARC layer (30) is etched using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using an isotropic etch having a selectivity of one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below 0.3 .mu.m. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).

대표청구항 ▼

[ What is claimed is:] [1.] A method of forming a polysilicon line, comprising the steps of:depositing a layer of polysilicon;depositing a layer of bottom anti-reflective coating (BARC) over the polysilicon layer;depositing a layer of resist over said BARC layer;removing portions of said resist layer using a lithographic tool to create a resist pattern having a width greater than or equal to a minimum lithographic limit of the lithographic tool;etching said BARC layer using said resist pattern until an endpoint is detected;isotropically overetching said BARC layer and said resist pattern using a timed etch that has a selectivity between the BARC layer and the resist pattern of one to one to create a reduced width pattern;etching said polysilicon layer using said reduced width pattern to create said polysilicon line.

이 특허에 인용된 특허 (9)

Nakamura Moritaka (Yokohama JPX) Kurimoto Takashi (Hashima JPX) Iizuka Katsuhiko (Kawasaki JPX), Dry etching with hydrogen bromide or bromine.
상세보기
Linliu Kung,TWX ; Cheng Hsu-Li,TWX ; Jeng Eric S.,TWX, Method for controlling linewidth by etching bottom anti-reflective coating.
상세보기
Ta Thuy B. (Austin TX), Method of etching anti-reflection coating.
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Auda Bernard (38 impasse de Guillelerville 91310 Linas/Montlhery FRX) Chanclou Roland (21 rue du Grand Moulin 77930 Perthes en Gatinais FRX), Method of producing high resolution and reproducible patterns.
상세보기
Ogawa Tohru (Kanagawa JPX), Process for production of micropattern utilizing antireflection film.
상세보기
Hashimoto Koichi (Kawasaki JPX) Ohtsuka Toshiyuki (Kawasaki JPX) Shinpuku Fumihiko (Kawasaki JPX) Matsunaga Daisuke (Kawasaki JPX) Enda Takayuki (Kawasaki JPX), Reduction of reflection by amorphous carbon.
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Babie Wayne T. (Poughkeepsie NY) Devries Kenneth L. (Hopewell Junction NY) Nguyen Bang C. (Wappingers Falls NY) Yang Chau-Hwa J. (Hopewell Junction NY), Selective silicon nitride plasma etching.
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Lee Young Hoon (Somers NY) Milkove Keith Raymond (Beacon NY) Stiebritz ; Jr. John William (Somers NY), Silicon etching method.
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Garza Mario (Sunnyvale CA), Techniques for uniformizing photoresist thickness and critical dimension of underlying features.
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이 특허를 인용한 특허 (26)

Bonser, Douglas J.; Purdy, Matthew; Hussey, Jr., James H., Dry isotropic removal of inorganic anti-reflective coating after poly gate etching.
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Iijima, Etsuo; Yamada, Norikazu, Dry-etching method.
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Iijima,Etsuo; Yamada,Norikazu, Dry-etching method.
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Chou,Pei Yu, Etching process and patterning process.
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Lee, Hyo-Jong; Son, Hong-Seong; Lee, Ui-Hyoung; Hah, Sang-Rok; Kim, In-Ryong; Kim, Yi-Gwon, Inductor for a system-on-a-chip and a method for manufacturing the same.
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Hu, Xiang; Wang, Helen; Sheikh, Arifuzzaman (Arif); Hichri, Habib; Wise, Richard, Integrated circuit system with reduced polysilicon residue and method of manufacture thereof.
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Nagarajan, Ranganathan; Mathew, Shajan; Bera, Lakshmi Kanta, Low temperature resist trimming process.
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Friedmann,James B.; Baum,Christopher C., Method for BARC over-etch time adjust with real-time process feedback.
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Jang,Jeong Yel; Lee,Kang Hyun, Method for fabricating a semiconductor device.
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Durcan, D. Mark; Doan, Trung T.; Lee, Roger; Keller, Dennis; Earl, Ren, Method for forming minimally spaced MRAM structures.
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Webb,Patrick R.; Zolla,Howard G., Method for forming thin film heads using a tri-layer anti-reflection coating for photolithographic applications and a structure thereof.
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Jang, Jeong Yel, Method for manufacturing semiconductor device.
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Brodsky,Colin J.; Allen,Scott D., Method for post lithographic critical dimension shrinking using thermal reflow process.
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Bonser, Douglas J.; Plat, Marina V.; Yang, Chih Yuh; Bell, Scott A.; Dakshina-Murthy, Srikanteswara; Fisher, Philip A.; Lyons, Christopher F., Method for semiconductor gate line dimension reduction.
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Bonser,Douglas J.; Plat,Marina V.; Yang,Chih Yuh; Bell,Scott A.; Dakshina Murthy,Srikanteswara; Fisher,Philip A.; Lyons,Christopher F., Method for semiconductor gate line dimension reduction.
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Wenge Yang ; Lewis Shen, Method for trimming a photoresist pattern line for memory gate etching.
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Lin Kevin,TWX ; Hao Ching-Chiao,TWX ; Lin Kun-Chi,TWX, Method of fabricating small dimension wires.
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Oguma, Hideki, Method of manufacturing semiconductor device.
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Laaksonen, Reima Tapani; Jacobs, Jarvis B., Method of photolithographically forming extremely narrow transistor gate elements.
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Durcan, D. Mark; Doan, Trung T.; Lee, Roger; Keller, Dennis; Earl, Ren, Minimally spaced MRAM structures.
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Durcan, D. Mark; Doan, Trung T.; Lee, Roger; Keller, Dennis; Earl, Ren, Minimally spaced MRAM structures.
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Tachikawa, Toshikazu; Kaneko, Fumitake; Kubota, Naotaka; Miyairi, Miwa; Hirosaki, Takako; Endo, Koutaro, Negative-working photoresist composition.
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Toshikazu Tachikawa JP; Fumitake Kaneko JP; Naotaka Kubota JP; Miwa Miyairi JP; Takako Hirosaki JP; Koutaro Endo JP, Negative-working photoresist composition.
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Lyons,Christopher F.; Plat,Marina V.; Dakshina Murthy,Srikanteswara; Bell,Scott A.; Tabery,Cyrus E., Patterning with rigid organic under-layer.
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Kruger,James Bernard; Snyder,Clint David; Webb,Patrick Rush; Zolla,Howard Gordon, Structure for photolithographic applications using a multi-layer anti-reflection coating.
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Reima Laaksonen ; Robert Kraft ; James B. Friedmann, Tunable gate linewidth reduction process.
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A	생활필수품
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A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Polysilicon linewidth reduction using a BARC-poly etch process 원문보기