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Stable delay buffer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03H-011/26
출원번호 US-0173701 (1998-10-15)
발명자 / 주소
  • Vikinski Omer,ILX
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 35  인용 특허 : 2

초록

An apparatus that includes a driver circuit and an active load circuit coupled to an output of the driver circuit. The active load circuit is configured to actively adjust the slew rate of a signal outputted by the driver circuit.

대표청구항

[ What is claimed is:] [1.] A circuit comprising:a driver circuit configured to output a signal;a load circuit coupled to the output of the driver circuit; andan active load circuit coupled to an output of the driver circuit, the active load circuit configured to actively adjust the slew rate of the

이 특허에 인용된 특허 (2)

  1. Baker William G., RC delay with feedback.
  2. Lee Teh-Kuin (San Jose CA), TTL delay matching circuit.

이 특허를 인용한 특허 (35)

  1. Wilcox, Jeffrey R.; Yosef, Noam; Yuffe, Marcelo, Apparatus and method for power efficient line driver.
  2. Wilcox, Jeffrey R.; Yosef, Noam; Yuffe, Marcelo, Apparatus and method for power efficient line driver.
  3. Matthew B. Haycock ; Stephen R. Mooney, Apparatus and methods for testing simultaneous bi-directional I/O circuits.
  4. Haycock, Matthew B.; Mooney, Stephen R., Apparatus for testing simultaneous bi-directional I/O circuits.
  5. Logue, John D.; Ching, Alvin Y.; Lu, Wei Guang, Automatic tap delay calibration for precise digital phase shift.
  6. Huber, Brian W., Circuit configuration for controlling signal propagation in fabricated devices.
  7. Brian W. Huber, Circuit configuration for enhancing performance characteristics of fabricated devices.
  8. Huber, Brian W., Circuit configuration for enhancing performance characteristics of fabricated devices.
  9. Takao Nakajima JP, Clock buffer circuit, and interface and synchronous type semiconductor memory device with clock buffer circuit.
  10. Mooney,Stephen R.; Casper,Bryan K., Clock recovery using clock phase interpolator.
  11. Carley,Adam L.; Allen,Daniel J.; Mandry,James E., Delay circuit for synchronizing arrival of a clock signal at different circuit board points.
  12. Shih Jeng Tzong,TWX, Delay circuit with voltage compensation.
  13. Okayasu,Toshiyuki; Suda,Masakatsu, Delay device, semiconductor testing device, semiconductor device, and oscilloscope.
  14. Morrison,Shawn K.; Pang,Raymond C., Digital clock manager capacitive trim unit.
  15. Stephen R. Mooney ; Matthew B. Haycock ; Aaron K. Martin ; Jonathan N. Spitz ; Michael S. Sandhinti, Digital variable-delay circuit having voltage-mixing interpolator and methods of testing input/output buffers using same.
  16. Carley,Adam L.; Allen,Daniel J.; Mandry,James E., Digitally programmable delay circuit with process point tracking.
  17. Carley,Adam L.; Allen,Daniel J.; Mandry,James E., Digitally programmable delay circuit with process point tracking.
  18. Mukker,Anoop; Bogin,Zohar; Freker,Dave; Dour,Navneet, Dynamically activated memory controller data termination.
  19. Huang, Yi-Cheng; Liu, Shang-Hsuan; Yang, Chou-Ying; Chang, Wei Kei; Feng, Hsin-Chang, Electronic device with PVT delay compensation and related method.
  20. Drost, Robert J.; Bosnyak, Robert J., Integrated circuit and method of adjusting capacitance of a node of an integrated circuit.
  21. Puckett, Joshua Lance, Inversely proportional voltage-delay buffers for buffering data according to data voltage levels.
  22. Puckett, Joshua Lance, Inversely proportional voltage-delay buffers for buffering data according to data voltage levels.
  23. Nagasue, Makoto, Master clock input circuit.
  24. Frederick, Jr., Marlin Wayne; Delk, Karen Lee; Ahlen, Lena; Dodrill, James Dennis, Method and apparatus for adjusting a timing derate for static timing analysis.
  25. To, Thomas; Hsu, Jen-Tai; Volk, Andrew M., Method and apparatus for local parameter variation compensation.
  26. Salim U. Chowdhury ; David Ray Bearden, Method and apparatus for placing repeaters in a network of an integrated circuit.
  27. Masleid, Robert Paul, Method and apparatus for process independent clock signal distribution.
  28. Frederick, Jr., Marlin Wayne; Delk, Karen Lee; Ahlen, Lena; Dodrill, James Dennis, Method for adjusting a timing derate for static timing analysis.
  29. Johnson,Phillip; Powell,Gary; Scholz,Harold, Noise-shielding, switch-controlled load circuitry for oscillators and the like.
  30. Kim, Kyo-hyoun; Chung, Dae-Hyun, Pulsed signal transition delay adjusting circuit.
  31. Chung,In Young, Semiconductor device having delay drift compensation circuit that compensates for delay drift caused by temperature and voltage variations in clock tree.
  32. Johnson, Gary M., Switched capacitor for a tunable delay circuit.
  33. Johnson, Gary M., Switched capacitor for a tunable delay circuit.
  34. Stephen R. Mooney ; Matthew B. Haycock, Symmetric, voltage-controlled CMOS delay cell with closed-loop replica bias.
  35. Morley, Kenneth S.; Cooklev, Todor; Gray, Mark; Gibbs, Darrin J., Video signal processing method and apparatus for internet appliances or embedded systems.
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