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Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03M-005/06
출원번호 US-0528659 (2000-03-20)
발명자 / 주소
  • Jusuf Gani
  • Sutardja Pantas
출원인 / 주소
  • Marvell International Ltd., BMX
대리인 / 주소
    Fenwick & West, LLP
인용정보 피인용 횟수 : 27  인용 특허 : 5

초록

Precompensated NRZ-encoded data for writing to magnetic storage medium operates with multiple NRZI-to-NRZ decoders that are each supplied with a selectably-variable version of a master clock. The delayed versions of the master clock are stably produced by delay elements operating with D-flip flops a

대표청구항

[ We claim:] [1.]1. A circuit for supplying a selected duration of delay with respect to transitions of a clock signal between first and second states thereof, the circuit comprising:a delay cell having inputs connected to receive the clock signal and a feedback signal for supplying an output signal

이 특허에 인용된 특허 (5)

  1. Flora Laurence P. (Covina CA) McCullough Michael A. (Pasadena CA), Automatic signal delay adjustment apparatus.
  2. Wojcicki Tomasz (Kanata CAX) Allan Graham (Stittsville CAX), Clock period dependent pulse generator.
  3. Jusuf Gani ; Sutardja Pantas, Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel.
  4. Murata David M. ; Bosnyak Robert J. ; Drost Robert J., System and method for serial to parallel data conversion using delay line.
  5. Gorecki James L. (Vail AZ) McGowan Michael J. (Tuscon AZ), Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in t.

이 특허를 인용한 특허 (27)

  1. Forster, Ian J.; King, Patrick F., Apparatus for forming a wireless communication device.
  2. Forster, Ian J.; King, Patrick F., Apparatus for preparing an antenna for use with a wireless communication device.
  3. Cho,Geun Hee; Kim,Kyu Hyoun, Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof.
  4. Chen, Shin Chung; Tso, Vincent Wing Sing, Loop filter capacitor multiplication in a charge pump circuit.
  5. Chaudhuri, Santanu; Dabral, Sanjay; Canagasaby, Karthisha, Low gain phase-locked loop circuit.
  6. Forster, Ian J; King, Patrick F, Manufacturing method for a wireless communication device and manufacturing apparatus.
  7. Cheng, Chi Fung, Method and apparatus for write precompensation in a magnetic recording system.
  8. Cheng, Chi Fung, Method and apparatus for write precompensation in a magnetic recording system.
  9. Cheng, Chi Fung, Method and apparatus for write precompensation in a magnetic recording system.
  10. Forster, Ian J; King, Patrick F, Method and system for manufacturing a wireless communication device.
  11. Cheng, Chi Fung, Method and system for precompensation of data output.
  12. Forster, Ian J.; King, Patrick F., Method and system for preparing wireless communication chips for later processing.
  13. Forster, Ian J.; King, Patrick F., Method of preparing an antenna.
  14. Forster,Ian J.; King,Patrick F., Method of producing a wireless communication device.
  15. Forster, Ian J; King, Patrick F, Method of producing antenna elements for a wireless communication device.
  16. Mathew, George; Lee, Yuan Xing; Song, Hongwei; Jingfeng, Liu; Park, Jongseung, Systems and methods for adaptive equalization in recording channels.
  17. Tan, Weijun; Fitzpatrick, Kelly, Systems and methods for area efficient noise predictive filter calibration.
  18. Mathew, George; Song, Hongwei; Lee, Yuan Xing, Systems and methods for dibit correction.
  19. Mueller, Brian K., Systems and methods for generating equalization data using shift register architecture.
  20. Huang, Jianzhong; Kou, Yu; Xia, Haitao; Jeong, Seongwook, Systems and methods for loop feedback.
  21. Cao, Rui; Kou, Yu; Wu, Xuebin; Han, Yang, Systems and methods for loop pulse estimation.
  22. Mathew, George; Lee, Yuan Xing; Song, Hongwei; Parker, David L.; Dziak, Scott M., Systems and methods for memory efficient signal and noise estimation.
  23. Wilson, Bruce; Mathew, George; Park, Jongseung, Systems and methods for multi-dimensional signal equalization.
  24. Mathew, George; Lee, Yuan Xing; Song, Hongwei, Systems and methods for on-the-fly write pre-compensation estimation.
  25. Mathew, George; Song, Hongwei; Lee, Yuan Xing, Systems and methods for timing and gain acquisition.
  26. Jin, Ming; Xia, Haitao, Systems and methods for track width determination.
  27. Ratnakar Aravind, Nayak; Bailey, James A.; Leonowich, Robert H., Systems and methods for two tier sampling correction in a data processing circuit.
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