초록 ▼

The present invention relates to a method of fabrication process which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor

The present invention relates to a method of fabrication process which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material. The semiconductor device contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region.

대표청구항 ▼

What is claimed is: 1. A method for forming a semiconductor device comprising: forming at least one field effect transistor (FET) on a substrate, wherein said at least one FET comprises a source region, a drain region, and a channel region; forming at least two trenches in said substrate, the first

What is claimed is: 1. A method for forming a semiconductor device comprising: forming at least one field effect transistor (FET) on a substrate, wherein said at least one FET comprises a source region, a drain region, and a channel region; forming at least two trenches in said substrate, the first of which stops at and exposes the source or drain region of the FET, and the second of which is adjacent to the FET and has a depth larger than that of the first trench; forming an outer metallic electrode layer and a dielectric layer for a trench capacitor in the second trench; and filling both the first and second trenches with a metallic material to concurrently form an inner metallic electrode layer for the trench capacitor and a metal contact for the FET. 2. The method of claim 1, wherein the FET is covered by at least one middle-of-line insulator layer and at least one dielectric capping layer before formation of the trenches. 3. The method of claim 1, wherein the inner metallic electrode layer of the trench capacitor and the metal contact of the field effect transistor comprise at least one metal or metal alloy selected from the group consisting of tungsten, copper, silver, and aluminum. 4. The method of claim 1, wherein during formation of the outer metallic electrode layer of the trench capacitor, a metallic strap is formed on a sidewall of the second trench, wherein said metallic strap is electrically connected to the source or drain region of the FET, and wherein the subsequently formed inner metallic electrode layer of the trench capacitor is electrically connected to the source or drain region of the FET by said metallic strap. 5. The method of claim 4, wherein the metallic strap comprises a metal silicide or a composite of metal silicide and metal nitride. 6. The method of claim 1, wherein the outer metallic electrode layer of the trench capacitor comprises a metal silicide or a silicidated metal nitride. 7. The method of claim 1, wherein the substrate comprises a semiconductor-on-insulator structure. 8. The method of claim 1, wherein the substrate comprises a bulk semiconductor structure. 9. The method of claim 1, wherein the metal contact of the FET is connected to a bitline, and wherein the inner metallic electrode layer of the trench capacitor is electrically isolated from said bitline. 10. A method of fabricating a semiconductor device comprising the steps of: forming at least one trench capacitor located in inner metallic electrode layer a trench in a substrate, said at least one trench capacitor comprising inner and outer metallic electrode layers with a dielectric layer therebetween; forming at least one field effect transistor (FET) located on said substrate, said at least one FET comprising a source region, a drain region, a channel region, and at least one metal contact connected to the source or drain region, wherein the inner metallic electrode layer of the trench capacitor and the metal contact of the FET comprise essentially the same metallic material; and forming at least one metallic strap beneath a top surface of said substrate and directly contacting both of said inner metallic electrode layer and one of said source region and said drain region, wherein a top surface of said inner metallic layer is located above said at least one metallic strap. 11. The method of claim 10, wherein the inner metallic electrode layer of the trench capacitor and the metal contact of the field effect transistor comprise at least one metal or metal alloy selected from the group consisting of tungsten, copper, silver, and aluminum. 12. The method of claim 10, wherein the metallic strap comprises a metal silicide or a silicidated metal nitride. 13. The method of claim 10, wherein the outer metallic electrode layer of the trench capacitor comprises a metal silicide or a composite of a metal silicide and a metal nitride. 14. The method of claim 10, wherein the dielectric layer of the trench capacitor comprises a high dielectric constant material having a dielectric constant of greater than 4. 15. The method of claim 10, wherein the substrate comprises a semiconductor-on-insulator structure. 16. The method of claim 10, wherein the substrate comprises a bulk semiconductor structure. 17. The method of claim 10, wherein the metal contact of the FET is connected to a bitline. 18. The method of claim 17, wherein the inner metallic electrode layer of the trench capacitor is electrically isolated from said bitline.