초록 ▼

A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduc

A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.

대표청구항 ▼

1. A method for determining a number of steps of a fine delay line (FDL) that are substantially equivalent to a step of a coarse delay line (CDL), the method comprising steps of: providing a clock signal;delaying the clock signal by a first delay substantially equivalent to a first predetermined del

1. A method for determining a number of steps of a fine delay line (FDL) that are substantially equivalent to a step of a coarse delay line (CDL), the method comprising steps of: providing a clock signal;delaying the clock signal by a first delay substantially equivalent to a first predetermined delay plus an adjustable number of steps of the FDL;delaying the clock signal by a second delay substantially equivalent to a second predetermined delay;adjusting the number of adjustable steps of the FDL so that the first delay is substantially equal to the second delay and providing a first number of adjustable steps of the FDL;delaying the clock signal by a third delay substantially equal to the second predetermined delay plus a step of the CDL;adjusting the number of adjustable steps of the FDL so that the first delay is substantially equal to the third delay and providing a second number of adjustable steps of the FDL; andsubtracting the first number from the second number of adjustable steps of the FDL to provide the number of steps of the FDL that are substantially equivalent to the step of the CDL. 2. A method as claimed in claim 1 wherein the step of delaying the clock signal by the first delay comprises a step of: delaying the clock signal by a delay substantially equal to in intrinsic delay of the FDL plus the adjustable number of steps of the FDL. 3. A method as claimed in claim 1 wherein the step of delaying the clock signal by the second delay comprises a step of: delaying the clock signal by a delay substantially equal to an intrinsic delay of the CDL. 4. A method as claimed in claim 1 wherein the step of adjusting the number of steps of the FDL so that the first delay is substantially equal to the second delay comprises steps of: adjusting the number of steps up if the first delay is less than the second delay; andadjusting the number of steps down if the first delay is greater than the second delay. 5. A method as claimed in claim 1 wherein the step of delaying the clock signal by the third delay comprises a step of: delaying the clock signal by a delay substantially equal to an intrinsic delay of the CDL plus the step of the CDL. 6. A method as claimed in claim 1 wherein the step of adjusting the number of steps of the FDL so that the first delay is substantially equal to the third delay comprises steps of: adjusting the number of steps up if the first delay is less than the third delay; andadjusting the number of steps down if the first delay is greater than the third delay. 7. A reference circuit for determining a number of steps of a fine delay line (FDL) that are substantially equivalent to a step of a coarse delay line (CDL), the reference circuit comprising: a FDL for receiving a clock signal, and for providing a first predetermined delay plus an adjustable number of delay steps,a CDL for receiving the clock signal, and for providing a second predetermined delay plus an adjustable number of delay steps,a phase detector for receiving outputs from the FDL and CDL and providing a phase difference of the outputs from the FDL and CDL, anda controller for: receiving the phase difference from the phase detector;providing a control signal to the CDL for setting a first number of steps of the CDL;providing a plurality of control signals for adjusting a first number of steps of the FDL so that a total delay of FDL is substantially equal to a total delay of the CDL;providing the control signal to the CDL for setting a second number of steps of the CDL wherein the second number of delay steps is equal to the first number of delay steps plus one;providing the plurality of control signals for adjusting a second number of steps of the FDL so that the total delay of FDL is substantially equal to the total delay of the CDL;subtracting the first number of steps of the FDL from the second number of steps of the FDL; andproviding the difference as the number of steps of the FDL that are substantially equivalent to the step of the CDL. 8. A reference circuit as claimed in claim 7 wherein the first predetermined delay is substantially equal to an intrinsic delay of the FDL. 9. A reference circuit as claimed in claim 7 wherein the second predetermined delay is substantially equal to an intrinsic delay of the CDL. 10. A reference circuit as claimed in claim 7 wherein the second predetermined delay is substantially greater than the first predetermined delay. 11. A delay-locked loop (DLL) comprising: a main coarse delay line (CDL) for delaying a main clock signal by zero or more steps of the coarse delay line,a main fine delay line (FDL) for further delaying the main clock signal by zero or more steps of the FDL, anda reference circuit for determining a number of steps of a fine delay line (FDL) that are substantially equivalent to a step of a coarse delay line (CDL), the reference circuit including: a FDL for receiving a clock signal, and for providing a first predetermined delay plus an adjustable number of delay steps;a CDL for receiving the clock signal, and for providing a second predetermined delay plus an adjustable number of delay steps;a phase detector for receiving outputs from the FDL and CDL and providing a phase difference of the outputs from the FDL and CDL; anda controller for: receiving the phase difference from the phase detector,providing a control signal to the CDL for setting a first number of steps of the CDL,providing a plurality of control signals for adjusting a first number of steps of the FDL so that a total delay of FDL is substantially equal to a total delay of the CDL,providing the control signal to the CDL for setting a second number of steps of the CDL wherein the second number of delay steps is equal to the first number of delay steps plus one,providing the plurality of control signals for adjusting a second number of steps of the FDL so that the total delay of FDL is substantially equal to the total delay of the CDL,subtracting the first number of steps of the FDL from the second number of steps of the FDL, andproviding the difference as the number of steps of the FDL that are substantially equivalent to the step of the CDL. 12. A DLL as claimed in claim 11 wherein the first predetermined delay is substantially equal to an intrinsic delay of the FDL. 13. A DLL as claimed in claim 11 wherein the second predetermined delay is substantially equal to an intrinsic delay of the CDL.