초록 ▼

A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device i

A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.

대표청구항 ▼

1. A non-volatile storage system, comprising: a substrate;a three dimensional memory array of memory cells positioned above the substrate;a plurality of word lines coupled to the memory cells;a plurality of global bit lines;a plurality of vertically oriented bit lines coupled to the memory cells; an

1. A non-volatile storage system, comprising: a substrate;a three dimensional memory array of memory cells positioned above the substrate;a plurality of word lines coupled to the memory cells;a plurality of global bit lines;a plurality of vertically oriented bit lines coupled to the memory cells; anda plurality of vertically oriented thin film transistor (TFT) select devices that are above the substrate, the vertically oriented TFT select devices are coupled between the vertically oriented bit lines and the global bit lines, when the vertically oriented TFT select devices are activated the vertically oriented bit lines are in communication with the global bit lines;each of the vertically oriented TFT select devices comprising: a first source/drain coupled to a first of the global bit lines;a second source/drain above the first source/drain and coupled to a first of the vertically oriented bit lines;a body having a first junction with the first source/drain and a second junction with the second source/drain;a gate having a top and a bottom relative to the substrate, either the first junction is below the bottom of the gate or the second junction is above the top of the gate; anda gate dielectric between the gate and the body. 2. The non-volatile storage system of claim 1, wherein the first junction is below the bottom of the gate relative to the substrate. 3. The non-volatile storage system of claim 2, further comprising control circuitry in communication with the global bit lines, the gates of the vertically oriented TFT select devices, and the word lines, the control circuitry applies voltages to the global bit lines, the gates of the vertically oriented TFT select devices, selected word lines, and unselected word lines to create a forward forming voltage for memory cells that are selected to undergo forming and to prevent a forming voltage for memory cells that are not to undergo forming. 4. The non-volatile storage system of claim 1, wherein the second junction is above the top of the gate relative to the substrate. 5. The non-volatile storage system of claim 4, further comprising control circuitry in communication with the global bit lines, the gates of the vertically oriented TFT select devices, and the word lines, the control circuitry applies voltages to the global bit lines, the gates of the vertically oriented TFT select devices, selected word lines, and unselected word lines to create a reverse forming voltage for memory cells that are selected to undergo forming and to prevent a forming voltage for memory cells that are not to undergo forming. 6. The non-volatile storage system of claim 1, wherein the gate is a first gate that is on one side of the body and the vertically oriented TFT select device comprises a second gate on the other side of the body, either the first junction is below the bottom of the second gate or the second junction is above the top of the second gate. 7. The non-volatile storage system of claim 1, wherein the body has a first conductivity, the first source/drain has a second conductivity that is opposite the first conductivity, and the second source/drain has the second conductivity. 8. The non-volatile storage system of claim 1, wherein the body has a first conductivity, the first source/drain has the first conductivity, and the second source/drain has the first conductivity. 9. A non-volatile storage system, comprising: a substrate;a three dimensional memory array of memory cells above the substrate, the memory cells being variable resistive memory elements;a plurality of word lines coupled to the memory cells;a plurality of global bit lines;a plurality of vertically oriented bit lines coupled to the memory cells; anda plurality of vertically oriented thin film transistor (TFT) select devices that are above the substrate;each of the vertically oriented TFT select devices comprising: a gate having a top and a bottom relative to the substrate;a first source/drain electrically coupled to a global bit line;a second source/drain electrically coupled to a vertical bit line;a channel region between the first source/drain and the second source/drain, the channel region extends vertically beyond either the top of the gate or the bottom of the gate; anda gate dielectric between the gate and the channel region. 10. The non-volatile storage system of claim 9, wherein the channel region extends vertically beyond the bottom of the gate relative to the substrate. 11. The non-volatile storage system of claim 10, further comprising control circuitry in communication with the global bit lines, the gates of the vertically oriented TFT select devices, and the word lines, the control circuitry applies voltages to the global bit lines, the gates of the vertically oriented TFT select devices, selected word lines, and unselected word lines to create a forward forming voltage for memory cells that are selected to undergo forming and to prevent a forming voltage for memory cells that are not to undergo forming. 12. The non-volatile storage system of claim 9, wherein the channel region extends vertically beyond the top of the gate relative to the substrate. 13. The non-volatile storage system of claim 12, further comprising control circuitry in communication with the global bit lines, the gates of the vertically oriented TFT select devices, and the word lines, the control circuitry applies voltages to the global bit lines, the gates of the vertically oriented TFT select devices, selected word lines, and unselected word lines to create a reverse forming voltage for memory cells that are selected to undergo forming and to prevent a forming voltage for memory cells that are not to undergo forming. 14. The non-volatile storage system of claim 9, wherein the channel region has a first conductivity, the first source/drain has a second conductivity that is opposite the first conductivity, and the second source/drain has the second conductivity. 15. The non-volatile storage system of claim 9, wherein the channel region has a first conductivity, the first source/drain has the first conductivity, and the second source/drain has the first conductivity. 16. The non-volatile storage system of claim 15, wherein the channel region has a first net doping concentration, the first source/drain and the second source/drain each have a second net doping concentration that is greater than the first net doping concentration. 17. A non-volatile storage system, comprising: a substrate;a monolithic three dimensional memory array of memory cells positioned above the substrate;a plurality of word lines connected together and coupled to a subset of the memory cells;a plurality of global bit lines;a plurality of vertically oriented bit lines coupled to the memory cells; anda plurality of vertically-asymmetric, vertically-oriented thin film transistor (TFT) select devices that are above the substrate, the vertically-oriented TFT select devices are coupled between the vertically oriented bit lines and the global bit lines;each of the vertically-asymmetric, vertically oriented TFT select devices comprising: a first source/drain electrically coupled to a global bit line of the plurality of global bit lines;a second source/drain electrically coupled to a bit line of the plurality of vertically oriented bit lines;a body having a first junction with the first source/drain and a second junction with the second source/drain;a gate having a top and a bottom relative to the substrate, the gate being offset with either its bottom being above the first junction relative to the substrate or its top being below the second junction relative to the substrate; anda gate dielectric between the gate and the body. 18. The non-volatile storage system of claim 17, wherein the first junction is below the bottom of the gate. 19. The non-volatile storage system of claim 18, further comprising control circuitry in communication with the global bit lines, the gates of the vertically oriented TFT select devices, and the word lines, the control circuitry applies voltages to a selected global bit line, unselected global bit lines, the gates of the vertically oriented TFT select devices, a selected word line, and unselected word lines to create a forward forming voltage for memory cells that are selected to undergo forming and to prevent a forming voltage for memory cells that are not to undergo forming, the voltage applied to the selected global bit line is greater than the voltage applied to the selected word line. 20. The non-volatile storage system of claim 17, wherein the second junction is above the top of the gate. 21. The non-volatile storage system of claim 20, further comprising control circuitry in communication with the global bit lines, the gates of the vertically oriented TFT select devices, and the word lines, the control circuitry applies voltages to a selected global bit line, unselected global bit lines, the gates of the vertically oriented TFT select devices, a selected word line, and unselected word lines to create a reverse forming voltage for memory cells that are selected to undergo forming and to prevent a forming voltage for memory cells that are not to undergo forming, the voltage applied to the selected global bit line is less than the voltage applied to the selected word line. 22. The non-volatile storage system of claim 17, wherein the first junction is a p-n junction, the second junction is a p-n junction. 23. The non-volatile storage system of claim 17, wherein the TFT is a depletion type device in which the body has a first conductivity, the first source/drain has the first conductivity, and the second source/drain has the first conductivity. 24. The non-volatile storage system of claim 17, wherein the plurality of vertically oriented bit lines have the same type of conductivity as the second source/drains.