High voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG)
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-027/092
H01L-021/8238
H01L-029/161
H01L-029/423
H01L-029/49
H01L-029/66
H01L-029/78
출원번호
16930547
(2020-07-16)
등록번호
11705455
(2023-07-18)
발명자
/ 주소
Kammler, Thorsten E.
Baars, Peter
출원인 / 주소
GLOBALFOUNDRIES U.S. INC.
대리인 / 주소
Canale, Anthony
인용정보
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0인용 특허 :
0
초록▼
The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a hig
The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material.
대표청구항▼
1. A structure, comprising: a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material comprising a first gate dielectric material and a second gate dielectric material, the second gate dielectric material comprising a thinner thickness than the
1. A structure, comprising: a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material comprising a first gate dielectric material and a second gate dielectric material, the second gate dielectric material comprising a thinner thickness than the first gate dielectric material; anda high-k dielectric material on the split-gate dielectric material. 2. The structure of claim 1, further comprising a plurality of high-k metal gate (HKMG) platform devices which includes the high-k dielectric material and at least one channel material. 3. The structure of claim 2, wherein the second gate dielectric material is on the HKMG platform devices and the at least one channel material comprises silicon germanium (SiGe). 4. The structure of claim 3, wherein the first gate dielectric material comprises a high voltage gate oxide and the second gate dielectric material comprises another gate oxide which is on the high voltage gate oxide. 5. The structure of claim 2, wherein the at least one channel material comprising SiGe includes a first SiGe channel formed in a first PFET device and a second SiGe channel formed in a second PFET device. 6. The structure of claim 5, wherein the first gate dielectric material and the second gate dielectric material are part of the plurality of EDMOS devices, and the EDMOS devices comprise a n-EDMOS device and a p-EDMOS device. 7. The structure of claim 6, wherein the high-k dielectric material is on the second gate dielectric material and a portion of the plurality of high-k metal gate (HKMG) platform devices is devoid of the first gate dielectric material and the second gate dielectric material. 8. The structure of claim 7, further comprising: a plurality of work function metals on the first gate dielectric material, the second gate dielectric material, and the high-k material; anda plurality of gates over the first gate dielectric material, the second gate dielectric material, and the high-k dielectric material. 9. The structure of claim 8, wherein the split gate dielectric material comprises a stepped feature between the first gate dielectric material and the second gate dielectric material. 10. The structure of claim 1, wherein the high voltage well comprises a n-well and a p-well. 11. The structure of claim 1, wherein the first gate dielectric material has a thickness in a range of 250 Å to 350 Å, and the second gate dielectric material has a thickness in the range of 30 Å to 70 Å. 12. A structure, comprising: a n-type extended drain MOSFET (n-EDMOS) device in an integrated circuit which includes a high-k dielectric material, a high voltage gate oxide, and another gate oxide;a p-type extended drain MOSFET (p-EDMOS) device in the integrated circuit which includes the high-k dielectric material, the high voltage gate oxide, and the another gate oxide;a plurality of high-k metal gate (HKMG) platform devices with the high-k dielectric material, the another gate oxide, and a channel material in the integrated circuit; anda stepped feature between the high voltage gate oxide and the another gate oxide. 13. The structure of claim 12, wherein the another gate oxide is a part of the HKMG platform devices and the channel material comprises silicon germanium (SiGe). 14. The structure of claim 13, wherein the channel material comprises a first SiGe channel formed in a first PFET device and a second SiGe channel formed in a second PFET device. 15. The structure of claim 14, wherein the another gate oxide is on the high voltage gate oxide. 16. The structure of claim 15, wherein the high-k dielectric material is on the another gate oxide. 17. The structure of claim 12, wherein the high voltage gate oxide has a thickness in a range of 250 Å to 350 Å. 18. The structure of claim 17, wherein the another gate oxide has the thickness in the range of 30 Å to 70 Å. 19. The structure of claim 12, further comprising: a plurality of work function metals on the high voltage gate oxide, the another gate oxide, and the high-k dielectric material; anda plurality of gates over the high voltage gate oxide, the another gate oxide, and the high-k dielectric material. 20. A method, comprising: forming a high voltage well in a semiconductor material;forming extended drain MOSFET (EDMOS) devices on the high voltage well with a split-gate oxide comprising a first gate oxide and a second gate oxide which has a thinner thickness than the first gate oxide; andforming high-k metal gate (HKMG) platform devices with a high-k dielectric material and at least one channel comprising silicon germanium (SiGe) comprising at least one of a thin oxide and a thick oxide in complementary metal-oxide-semiconductor (CMOS) field effect transistors.
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