[논문]Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope

Najam, Faraz; Kim, Sangsig; Yu, Yun Seop

doi:10.5573/jsts.2013.13.5.530

[국내논문] Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope 원문보기

Journal of semiconductor technology and science, v.13 no.5, 2013년, pp.530 - 537

Najam, Faraz (School of Electrical Engineering, Korea University) , Kim, Sangsig (School of Electrical Engineering, Korea University) , Yu, Yun Seop (Department of Electrical, Electronic and Control Engineering and IITC, Hankyong National University)

Abstract ▼ AI-Helper

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

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제안 방법

The scaling theory presented in [2] investigates design constraints of GAAMOSFET devices. The study determines device dimensions including silicon channel radius R and dielectric thickness t_ox (essential in controlling the SCEs inherent in the device) necessary to maintain an acceptable subthreshold slope (SS) performance of the device. However, this scaling scheme is for ideal surrounding gate devices; the theory neglects the impact of interface trap charge on GAAMOSFET device SS performance.

이론/모형

The model is iterative and does not consider channel doping concentration. In this study we present an explicit, non-iterative surface potential calculation-method that simultaneously takes into account interface trap states as well as channel-doping concentration in surface potential calculation of GAAMOSFET. The model is presented in section II and verified extensively by 3D numerical simulation.
The model is presented in section II and verified extensively by 3D numerical simulation. The results from the model are used to find the qualitative and quantitative impact of interface trap charge on SS degradation (Section III) (by using our previously reported extracted interface trap charge values) by employing the aforementioned scaling theory. Design constraints of GAAMOSFET device are investigated with emphasis on the effect of interface trap charge on device SS performance.
2. Drift-Diffusion transport model, constant mobility model, Fermi-Dirac statistics, and Shockley-Read-Hall recombination model were used in the simulation. Fig.
Design constraints of GAAMOSFET device with emphasis on the impact of interface trap on devices’ SS were discussed, by employing a GAAMOSFET scaling theory.

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