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[국내논문] An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications 원문보기

Journal of electrical engineering & technology, v.9 no.1, 2014년, pp.247 - 253  

Arun Samuel, T.S. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering) ,  Balamurugan, N.B. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering)

Abstract ▼ AI-Helper 아이콘AI-Helper

In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expres...

Keyword

#Tunnel field effect transistor (TFET)   #Band to band Tunnelling   #Poisson equation   #Surface potential   #Electric field  

AI 본문요약
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제안 방법

  • In this paper, we propose a new analytical model for DMDG TFET structure which enhances the ION current during device operation. The aim of this work is, to study the potential benefits offered by the DMDG TFET by using parabolic approximation technique for the first time, which is simple and accurate.
  • current during device operation. The aim of this work is, to study the potential benefits offered by the DMDG TFET by using parabolic approximation technique for the first time, which is simple and accurate. The analytical model is developed using two dimensional solution of Poisson equation.

이론/모형

  • This model is used to calculate the surface potential and electric field distribution in the device under the two metal gates and the drain current IDS is derived from the electric field using Kane’s model.
  • The aim of this work is, to study the potential benefits offered by the DMDG TFET by using parabolic approximation technique for the first time, which is simple and accurate. The analytical model is developed using two dimensional solution of Poisson equation. This model is used to calculate the surface potential and electric field distribution in the device under the two metal gates and the drain current IDS is derived from the electric field using Kane’s model.
  • The tunnelling generation rate (G) can be calculated using Kane’s model.
  • The analytical model is based on two-dimensional Poisson’s equation solved using parabolic approximation.
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참고문헌 (25)

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    상세보기 crossref

  2. Abhijit Mallik, Avik Chattopadhyay, "The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High- ${\kappa}$ Gate Dielectric", IEEE Trans. Electron Devices, Vol. 59, No. 2, pp.277-282, Feb.2012 

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  9. T.S. Arun Samuel, N.B. Balamurugana, S. Bhuvaneswari, D. Sharmilaa & K. Padmapriyaa, "Analytical modelling and simulation of single-gate SOI TFET for low-power applications" International Journal of Electronics, Published online on July.2013. DOI:10.1080/00207217.2013.796544 

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  10. Anne S. Verhulst, William G. Vandenberghe, Karen Maex, and Guido Groeseneken, "Tunnel field-effect transistor without gate-drain overlap", Applied Physics Lett., Vol. 91, No. 5, pp. 053102-053105, Jul. 2007. 

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  14. L. Wang, E. Yu, Y. Taur and P. Asbeck, "Design of tunneling field effect transistors based on staggered hetero junctions for ultra low power applications," IEEE Electron Device Lett., Vol. 31, No. 5, pp- 431-433, May.2010. 

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  15. O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt and D. A. Antoniadis, "Design of Tunneling Field-Effect Transisitors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions," IEEE Electron Device Lett., Vol. 29, No. 9, pp- 1074-1077, Sep. 2008. 

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  19. Bardon MG, Neves HP, Puers R, and Hoof CV, Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions," IEEE Trans. Electron Devices, Vol.57, No.4, pp. 827-34, Apr.2010. 

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  20. A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, "Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization," Journal of Applied Physics, Vol. 104, No. 6 pp. 064 514-1,Sep. 2008. 

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  21. Min jin Lee,"Analytical Model of a single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs)," Solid-State Electronics, Vol. 63, pp. 110-114, Sep. 2011. 

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  22. Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, "Assessment of ambipolar behaviour of a tunnel FET and Influence of Structural Modifications" Journal of Semiconductor Technology and Science, Vol.12, No.4, pp.482-491, Dec.2012. 

    원문보기 상세보기 crossref

  23. E.O. Kane, "Zener tunneling in semiconductors," J.Phys. Chem. Solides, Vol.12, No.2, pp 181-188, Jan. 1960. 

    상세보기 crossref

  24. E.O. Kane, "Theory of tunneling," J. Appl. Phys., Vol. 32, No. 1, pp. 83-91, Jan.1961. 

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  25. Sentaurus Device User Guide, Synopsys Inc., Version D-2010.03. 

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