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[국내논문] Analytical Surface Potential Model with TCAD Simulation Verification for Evaluation of Surrounding Gate TFET 원문보기

Journal of electrical engineering & technology, v.9 no.2, 2014년, pp.655 - 661  

Samuel, T.S. Arun (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering) ,  Balamurugan, N.B. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering) ,  Niranjana, T. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering) ,  Samyuktha, B. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering)

Abstract AI-Helper 아이콘AI-Helper

In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surf...

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가설 설정

  • (b) The electric field in the center of the silicon pillar is zero.
  • (c) The electric field at the silicon / oxide interface is continuous.
  • (a) The surface potential φs (z) is a function of z only.
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참고문헌 (20)

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  2. T. K. Chiang, "A new two-dimensional threshold Voltage model for cylindrical, fully depleted surrounding- gate (SG) MOSFETs" Microelectronics Reliability, Vol. 47, pp. 379-383, 2007. 

  3. N.B. Balamurugan, K.Sankaranarayanan, and M. Fathima John," 2DTransconductance to Drain Current Ratio Modeling of Dual Material Surrounding Gate Nanoscale SOI MOSFETs", Journal of Semiconductor Technology and Science, Vol.9, No.2, Jun., 2009. 

  4. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, "Band-to-band tunneling in carbon nanotube fieldeffect transistors," Phys. Rev. Lett., vol. 93, no. 19, pp. 196805-1-196,805-4, Nov., 2004. 

  5. K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the vertical tunnel FET with tunnel band gap modulation and gate work function engineering," IEEE Transactions on Electron Devices, Vol. 52, No. 5, pp. 909-917, May., 2005. 

  6. L. Wang, E. Yu, Y. Taur and P. Asbeck, "Design of tunneling field effect transistors based on staggered hetero junctions for ultra low power applications," IEEE Electron Device Lett., Vol. 31, No. 5, pp- 431-433,May., 2010. 

  7. O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt and D. A. Antoniadis, "Design of Tunneling Field-Effect Transisitors Using Strained- Silicon/Strained-Germanium Type-II Staggered Heterojunctions," IEEE Electron Device Lett., Vol. 29, No. 9, pp- 1074-1077, Sep., 2008. 

  8. J. Appenzeller, Y. M. Lin, J. Knoch, Z. H. Chen, and P. Avouris, "Comparing carbon nanotube transistors The ideal choice: A novel tunneling device design," IEEE Transactions on Electron Devices,, Vol. 52, No. 12, pp. 2568-2576,Dec., 2005. 

  9. K. Boucart and A. M. Ionescu, "Double-gate tunnel FET with high- k gate dielectric," IEEE Transactions on Electron Devices, Vol. 54, No. 7, pp. 1725-1733, Jul., 2007. 

  10. T.S.Arun samuel et al., "Analytical Modeling and Simulation of Dual Material Gate Tunnel Field Effect Transistors" accepted for Journal of Electrical Engineering and Technology. http://www.jeet.or.kr/LTKPSWeb/uploadfiles/be/201307/230720131632073035000.pdf 

  11. Sneh Saurabh and M. Jagadesh Kumar, "Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor," IEEE Transactions on Electron Devices, Vol. 58, No. 2, pp. 404-410, Feb., 2011. 

  12. C. Sandow, J. Knoch, C. Urban, Q.-T. Zhao, and S. Mantl, "Impact of electrostatics and doping concentration on the performance of silicon tunnel fieldeffect transistors," Solid-State Electronics, vol. 53, no. 10, pp.1126-1129, Oct., 2009. 

  13. Min jin Lee," Analytical Model of a single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs)," Solid-State Electronics, Vol. 63, pp. 110-114, Sep., 2011. 

  14. W. Vandenberghe, A. Verhulst, G. Groeseneken, B. Soree, and W. Magnus, "Analytical Model for Point and Line Tunneling in a Tunnel Field-Effect Transistor," in Proc. SISPAD, 2008, pp. 137-140. 

  15. A. S. Verhulst, B. Soree, D. Leonelli, W. G. Vandenberghe, G. Groeseneken, "Modeling the single-gate, double-gate, and gate-all-around tunnel field effect transistor," J. Appl. Phys, Vol. 107, No. 2, pp. 024518, Feb., 2010. 

  16. M.G. Bardon,H.P. Neves, R.Puers, and C.V Hoof, "Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions," IEEE Trans., on Electron Devices, Vol. 57, No. 4, pp. 827-34, Apr., 2010. 

  17. A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, "Boosting the on-current of a nchannel nanowire tunnel field-effect transistor by source material optimization," J. Appl. Phys., Vol. 104, No. 6, pp. 064 514-1, Sep., 2008. 

  18. E.O. Kane, "Zener tunneling in semiconductors," J.Phys. Chem.Solides, Vol. 12, No. 2, pp. 181-188, Jan. 1960. 

  19. E.O. Kane, "Theory of tunneling," J. Appl. Phys., Vol. 32, No. 1, pp. 83-91, Jan. 1961. 

  20. Sentaurus Device User Guide, Synopsys Inc., Version D-2010.03. 

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