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Impact of Energy Relaxation of Channel Electrons on Drain-Induced Barrier Lowering in Nano-Scale Si-Based MOSFETs 원문보기

ETRI journal, v.39 no.2, 2017년, pp.284 - 291  

Mao, Ling-Feng (School of Computer & Communication Engineering, University of Science & Technology Beijing)

Abstract ▼ AI-Helper 아이콘AI-Helper

Drain-induced barrier lowering (DIBL) is one of the main parameters employed to indicate the short-channel effect for nano metal-oxide semiconductor field-effect transistors (MOSFETs). We propose a new physical model of the DIBL effect under two-dimensional approximations based on the energy-conserv...

주제어

#Energy conservation   #MOSFETs   #Drain-induced barrier lowering  

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제안 방법

  • In conclusion, we proposed a new physical model of DIBL based on the energy balance of channel electrons under 2D approximations. First, we deduced the formula of the channel field at the source using a 2D model, and we then used the energy balance to determine the increased energy caused by the channel field. Finally, we obtained an analytical expression for the DIBL coefficient.
  • In this study, we used the energy-conservation equation, and there was a reduction in the effective barrier height between the source and the channel, which is calculated from the channel electrons, when the channel electrons gain kinetic energy from the channel field. This model illustrates the physical origin of such a DIBL based on its simplicity and analytic nature.
  • The data of the DIBL coefficient versus temperature were obtained from [27]. The above results further demonstrate that the proposed model is suitable for describing the physical origin of DIBL in Si-based MOSFETs.

데이터처리

  • To further test the validity of the proposed model, we compared the doping concentration and temperature-dependent DIBL coefficient. The DIBL coefficient has been found to first decrease and then increase with the channel doping concentration [24].
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참고문헌 (27)

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  2. S. Bangsaruntip et al., "Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10 nm Node and Beyond," IEEE Int. IEDM, Washington, DC, USA, Dec. 9-11, 2013, pp. 20.2.1-20.2.4. 

  3. J.H. Huang et al., "A Physical Model for MOSFET Output Resistance," IEDM Tech. Dig., San Francisco, CA, USA, Dec. 13-16, 1992, pp. 569-572. 

  4. M.J. Deen and Z.X. Yan, "DIBL in Short-Channel NMOS Devices at 77 K," IEEE Trans. Electron. Devices, vol. 39, no. 4, Apr. 1992, pp. 908-915. 

    상세보기 crossref

  5. I. Ferain, C.A. Colinge, and J.P. Colinge, "Multigate Transistors as the Future of Classical Metal-Oxide-Semiconductor Field-Effect Transistors," Nature, vol. 479, no. 7373, Nov. 2011, pp. 310-316. 

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  6. S. Narasimha et al., "22 nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL," IEEE Int. IEDM Tech. Dig., San Francisco, CA, USA, Dec. 10-13, 2012, pp. 3.3.1-3.3.4. 

  7. L.F. Mao, H. Ning, and J.Y. Wang, "The Current Collapse in AlGaN/GaN High-Electron Mobility Transistors Can Originate from the Energy Relaxation of Channel Electrons," PloS one, vol. 10, no. 6, June 2016, pp. 1-9. 

  8. L.F. Mao et al., "Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors," Sci. Rep., vol. 5, Dec. 2015, pp. 1-11. 

  9. L.F. Mao et al., "Physical Modeling of Activation Energy in Organic Semiconductor Devices Based on Energy and Momentum Conservations," Sci. Rep., vol. 6, Apr. 2016, pp. 1-12. 

    상세보기 crossref

  10. V.T. Dolgopolov et al., "Energy Relaxation Time in a Two-Dimensional Electron Gas at a (001) Surface of Silicon," J. Experimental Theoretical Phy., vol. 62, no. 6, Dec. 1985, pp. 1219-1224. 

  11. N. Balkan, Hot Electrons in Semiconductors: Physics and Devices, Oxford, UK: Oxford University Press, 1998, p. 385. 

  12. C. Canali et al., "Electron and Hole Drift Velocity Measurements in Silicon and Their Empirical Relation to Electric Field and Temperature," IEEE Trans. Electron. Devices, vol. 22, no. 11, Nov. 1975, pp. 1045-1047. 

    상세보기 crossref

  13. C.G. Sodini, P.K. Ko, and J.L. Moll, "The Effect of High Fields on MOS Device and Circuit Performance," IEEE Trans. Electron. Devices, vol. 31, no. 10, Oct. 1984, pp. 1386-1393. 

    상세보기 crossref

  14. S.M. Sze and K.K. Ng, Physics of Semiconductor Devices, 3rd ed. Hoboken, NJ, USA: Wiley, 1996. 

  15. A. Ruangphanit et al., "Substrate Bias Effects on Drain Induced Barrier Lowering (DIBL) in Short Channel NMOS FETs," Australian J. Basic Appl. Sci., vol. 3, no. 3, July 2009, pp. 1640-1644. 

  16. A. Ruangphanit, M. Rangson, and V. Poyai, "The Parameters Mismatch Model of Threshold Voltage for the Narrow and Short Channel MOSFET," J. Appl. Sci. Res., vol. 3, no. 1, Jan. 2006, pp. 13-16. 

  17. K.K. Young, "Short-Channel Effect in Fully Depleted SOI MOSFETs," IEEE Trans. Electron. Devices, vol. 36, no. 2, Feb. 1989, pp. 399-402. 

    상세보기 crossref

  18. S. Lee et al., "SPICE-Compatible New Silicon Nanowire Field-Effect Transistors (SNWFETs) Model," IEEE Trans. Nanotechnol., vol. 8, no. 5, Oct. 2009, pp. 643-649. 

    상세보기 crossref

  19. R. Muanghlua, N. Vittayakorn, and A. Ruangphanit, "Channel Engineering for Submicron N-Channel MOSFET Based on TCAD Simulation," Australian J. Basic Appl. Sci., vol. 2, no. 3, Jan. 2008, pp. 406-411. 

  20. K. Aoki, Nonlinear Dynamics and Chaos in Semiconductors, Boca Raton, FL, USA: CRC Press, 2000, p. 38. 

  21. A.J. Sabbah and D.M. Riffe, "Femtosecond Pump-Probe Reflectivity Study of Silicon Carrier Dynamics," Phys. Rev. B, vol. 66, no. 16, Oct. 2002, p. 165217. 

    상세보기 crossref

  22. H. Batwani, M. Gaur, and M.J. Kumar, "Analytical Drain Current Model for Nanoscale Strained-Si/SiGe MOSFETs," Int. J. Comput. Math. Electr. Electron. Eng., vol. 28, no. 2, Mar. 2009, pp. 353-371. 

    상세보기 crossref

  23. C. Jacoboni et al., "A Review of Some Charge Transport Properties of Silicon," Solid-State Electron., vol. 20, no. 2, Feb. 1977, pp. 77-89. 

    상세보기 crossref

  24. M. Singh and A.K. Rana, "Study of Short Channel Effects on FDSOI MOSFET in Nano Regime-TCAD Simulation," ITSI TEEE, vol. 1, no. 6, Dec. 2013, pp. 27-30. 

  25. S.C. Brugger and A. Schenk, "First-Principle Computation of Relaxation Times in Semiconductors for Low and High Electric Fields," Int. Conf. Simulation Semicond. Process. Devices, Tokyo, Japan, Sept. 1-3, 2005, pp. 151-154. 

  26. K. Chain et al., "A MOSFET Electron Mobility Model of Wide Temperature Range (77-400 K) for IC Simulation," Semicond. Sci. Technol., vol. 12, no. 4, Apr. 1997, pp. 355-359. 

    상세보기 crossref

  27. O. Semenov, A. Vassighi, and M. Sachdev, "Leakage Current in Sub-quarter Micron MOSFET: a Perspective on Stressed Delta I DDQ Testing," J. Electron. Test., vol. 19, no. 3, June 2003, pp.341-352. 

    상세보기 crossref

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