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NTIS 바로가기한국정보전자통신기술학회논문지 = Journal of Korea institute of information, electronics, and communication technology, v.13 no.1, 2020년, pp.48 - 57
김영희 (Department of Electronic Engineering, Changwon National University) , 차재한 (SK hynix system ic INC.) , 김홍주 (Department of Electronic Engineering, Changwon National University) , 이도규 (Department of Electronic Engineering, Changwon National University) , 하판봉 (Department of Electronic Engineering, Changwon National University) , 박무훈 (Department of Electronic Engineering, Changwon National University)
MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single ...
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F. Xu, X. Q. He, L. Zhang, "Key Design Techniques of A 40ns 16K Bits Embedded EEPROM Memory", 2004 International Conference on Communications, Circuits and Systems, vol. 2, pp. 1516-1520, June 2004.
A. Conte, G. L. Gudiceo, G. Palumbo, A. Signorello, "A High-Performance Very Low-Voltage Current Sense Amplifier for Nonvolatile Memory", IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 507-514, Feb. 2005.
H. Hidaka, "Embedded Flash Memory for Embedded Systems: Technology, Deign for Sub-systems, and Innovations," Springer International Publishing, 2017.
M. Hatanaka et al., "Value Creation in SOC/MCU Applications by Embedded Non-Volatile Memory Evolutions," Asian Solid State Circuits Conference, pp. 38-42, Nov. 2007.
G. S. Cho, et al., "Design of a Small-Area Low-Power, and High-Speed 128-KBit EEPROM IP for Touch Screen Controllers," Journal of KIIC, vol. 13, no. 12, pp. 2633-2640, Dec. 2009.
Heon Park et al., "Design of a Cell Verification Module for Large-Density EEPROMs," JKIIECT, vol. 10, no. 2, pp. 176-183, Oct. 2017.
Y. H. Kim et al., "Design of an Embedded Flash IP for USB Type-C Applications," JKIIECT, vol. 12, no. 3, pp. 312-320, June 2019.
Y. H. Kim et al., "Design of 40ns 512Kb EEPROM IP," Proceedings of the 4th ICIECT 2018, pp. 245-246, July 2018.
Y. H. Kim et al.,"Study on Memory Circuit Structure Analysis," ETRI Report, Oct. 2017.
Y. K Ha et al., "Design of Zero-Layer FTP Memory IP," JKIIEC , vol. 11, no. 6, pp. 742-750, Dec. 2018.
Chih-Ping, Chung and Kuei-Shu Chang-Liao. "A highly scalable single poly-silicon embedded electrically erasable programmable read only memory with tungsten control gate by full CMOS process." IEEE Electron Device Letters, vol. 36, no. 4, pp. 336-338, Feb. 2015.
Y. Roizin et al., "High density MTP logic NVM for power management applications," IEEE International memory workshop, pp. 1-2, June 2009.
J. S. Hu et al., "A DC-DC Converter IP Design using a Multi-Phase Charge Pumping Scheme," ITC-CSCC, pp. 539-542, 2004.
P, Favrat, "A High-Efficiency CMOS Voltage Doubler", IEEE JSSC, vol. 33, no. 3, pp. 410-416, Mar. 1998.
G. H. Lim et. al., "Charge pump design for TFT-LCD driver IC using stack-MIM capacitor," IEICE Trans on Electronics, vol. E91-C, no. 6, pp. 928-935, June 2008.
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