최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기전자통신동향분석 = Electronics and telecommunications trends, v.36 no.3, 2021년, pp.12 - 22
문제현 (플렉시블전자소자연구실) , 남수지 (플렉시블전자소자연구실) , 주철웅 (플렉시블전자소자연구실) , 성치훈 (플렉시블전자소자연구실) , 김희옥 (실감디스플레이연구실) , 조성행 (플렉시블전자소자연구실) , 박찬우 (플렉시블전자소자연구실)
Since the technical realization of self-aligned planar complementary metal-oxide-semiconductor field-effect transistors in 1960s, semiconductor manufacturing has aggressively pursued scaling that fruitfully resulted in tremendous advancement in device performances and realization of features sizes s...
G.E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, Apr. 1965, pp. 114-117.
R. Courtland, "Transistors could stop shrinking in 2021," IEEE Spectrum, vol. 53, no. 9, Sept. 2016, pp. 9-11, doi: 10.1109/MSPEC.2016.7551335.
M.T. Bohr and I.A. Young, "CMOS scaling trends and beyond," IEEE Micro, vol. 37, no. 6, Nov./Dec. 2017, pp. 20-29, doi: 10.1109/MM.2017.4241347.
Samsung Newsroom, "Samsung's new 3D integration technology X-Cube(eXtended-Cube)," 2020, Samsung, https://news.samsung.com/global/samsung-announces-availability-of-its-silicon-proven-3d-ic-technology-for-high-performance-applications.
S. Salahuddin, K. Ni, and S. Datta, "The era of hyper-scaling in electronics," Nature Electron., vol. 1, 2018, pp. 442-450.
S. Datta et al., "Back-end-of-line compatible transistors for monolithic 3-D integration," IEEE Micro, vol. 39, no. 6, Nov./Dec. 2019, pp. 8-15, doi: 10.1109/MM.2019.2942978.
Y. Son et al., "Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process," Nat. Electron., vol. 2, 2019, pp. 540-548.
Sony Semiconductor Solutions Corporation, "3-layer stacked CMOS image sensor with DRAM for smartphones," Sony Corporation, 2017, https://www.sony.net/SonyInfo/News/Press/201702/17-013E/
*원문 PDF 파일 및 링크정보가 존재하지 않을 경우 KISTI DDS 시스템에서 제공하는 원문복사서비스를 사용할 수 있습니다.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.