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첨단 반도체 패키징을 위한 미세 피치 Cu Pillar Bump 연구 동향
Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging 원문보기

마이크로전자 및 패키징 학회지 = Journal of the Microelectronics and Packaging Society, v.30 no.3, 2023년, pp.1 - 10  

노은채 (충북대학교 신소재공학과) ,  이효원 (충북대학교 신소재공학과) ,  윤정원 (충북대학교 신소재공학과)

초록
AI-Helper 아이콘AI-Helper

최근, 고사양 컴퓨터, 모바일 제품의 수요가 증가하면서 반도체 패키지의 고집적화, 고밀도화가 요구된다. 따라서 많은 양의 데이터를 한 번에 전송하기 위해 범프 크기 및 피치 (Pitch)를 줄이고 I/O 밀도를 증가시킬 수 있는 플립 칩 (flip-chip), 구리 필러 (Cu pillar)와 같은 마이크로 범프 (Micro-bump)가 사용된다. 하지만 범프의 직경이 70 ㎛ 이하일 경우 솔더 (Solder) 내 금속간화합물 (Intermetallic compound, IMC)이 차지하는 부피 분율의 급격한 증가로 인해 취성이 증가하고, 전기적 특성이 감소하여 접합부 신뢰성을 악화시킨다. 따라서 이러한 점을 개선하기 위해 UBM (Under Bump Metallization) 또는 Cu pillar와 솔더 캡 사이에 diffusion barrier 역할을 하는 층을 삽입시키기도 한다. 본 review 논문에서는 추가적인 층 삽입을 통해 마이크로 범프의 과도한 IMC의 성장을 억제하여 접합부 특성을 향상시키기 위한 다양한 연구를 비교 분석하였다.

Abstract AI-Helper 아이콘AI-Helper

Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch...

주제어

표/그림 (17)

참고문헌 (55)

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