$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

인공지능 반도체 및 패키징 기술 동향
Artificial Intelligence Semiconductor and Packaging Technology Trend 원문보기

마이크로전자 및 패키징 학회지 = Journal of the Microelectronics and Packaging Society, v.30 no.3, 2023년, pp.11 - 19  

김희주 (서울시립대학교 신소재공학과) ,  정재필 (서울시립대학교 신소재공학과)

초록
AI-Helper 아이콘AI-Helper

최근 Chat GPT와 같은 인공지능 (Artificial Intelligence, AI) 기술의 급격한 발전에 따라 AI 반도체의 중요성이 강조되고 있다. AI 기술은 빅데이터 처리, 딥 러닝, 알고리즘 등의 요구사항으로 인해 대용량 데이터를 빠르게 처리할 수 있는 능력을 필요로 한다. 그러나 AI 반도체는 대규모 데이터를 처리하는 과정에서 과도한 전력 소비와 데이터 병목현상 문제가 발생한다. 반도체 전공정의 초미세공정이 물리적 한계에 도달함에 따라, AI 반도체의 연산을 위한 최신 패키징 기술이 요구되는 추세이다. 본 고에서는 AI 반도체에 적용가능한 인터포저, TSV, 범핑, Chiplet, 하이브리드 본딩 패키징 기술에 대해서 기술하였다. 이러한 기술들은 AI 반도체의 전력 효율과 연산 속도를 향상시키는데 기여할 것으로 기대된다.

Abstract ▼ AI-Helper 아이콘AI-Helper

Recently with the rapid advancement of artificial intelligence (AI) technologies such as Chat GPT, AI semiconductors have become important. AI technologies require the ability to process large volumes of data quickly, as they perform tasks such as big data processing, deep learning, and algorithms. ...

주제어

#Artificial Intelligence (AI)   #2   #5-dimensional packaging   #Through-Si-Via (TSV)   #Chiplet   #Hybrid bonding  

표/그림 (8)

참고문헌 (45)

  1. WIPO, "WIPO Technology Trends 2019; Artificial Intelligence", 40 (2020) 

  2. S. M. Viswanathan, "AI Chips: New Semiconductor Era",？International Journal of Advanced Research in Science",？Engineering and Technology, 7(8), 14687-14694 (2020). 

  3. C. H. Yu, L. J. Yen, C. Y. Hsieh, J. S. Hsieh, Victor C. Y.？Chang, C. H. Hsieh, C. S. Liu, C. T. Wang, KC Yee, and？Doug C. H. Yu, "High Performance, High Density RDL for？Advanced Packaging", IEEE 68th Electronic Components？and Technology Conference (ECTC), 587-593 (2018). 

  4. G. Shan, Y. Zheng, C. Xing, D. Chen, G. Li, and Y. Yang,？"Architecture of computing system based on chiplet", Micromachines, 13(2), 105 (2022). 

    상세보기

  5. A. Kayid, Y. Khaled, and M. Elmahdy, "Performance of cpus/gpus for deep learning workloads", Media Engineering and？Technology Faculty, German University in Cairo (2018). 

  6. B. Li, J. Gu, and W. Jiang, "Artificial Intelligence (AI) Chip？Technology Review", 2019 International Conference on Machine？Learning, Big Data and Business Intelligence (MLBDBI),？Taiyuan, China, 114-117 

  7. Y. R. Jeong, K. Cho, Y. Jeong, S. B. Kwon, and S. E. Lee,？"A Real-Time Reconfigurable AI Processor Based on FPGA",？2023 IEEE International Conference on Consumer Electronics？(ICCE), Las Vegas, NV, USA, 1-2 (2023). 

  8. L. Yang, Z. Yan, M. Li, H. Kwon, L. Lai, T. Krishna, V. Chandra,？W. Jiang, and Y. Shi, "Co-Exploration of Neural Architectures？and Heterogeneous ASIC Accelerator Designs Targeting？Multiple Tasks", 2020 57th ACM/IEEE Design Automation？Conference (DAC), San Francisco, CA, USA, 1-6 (2020). 

  9. S. Dutta, H. Jeong, Y. Yang, V. Cadambe, T. M. Low and P.？Grover, "Addressing Unreliability in Emerging Devices and？Non-von Neumann Architectures Using Coded Computing",？Proceedings of the IEEE, 108(8), 1219-1234 (2020). 

  10. H. Kim, S. Baek, J. Song, and T. Song, "A Novel Processing？Unit and Architecture for Process-In Memory (PIM) in？NAND Flash Memory", 2022 19th International SoC Design？Conference (ISOCC), 127-128 (2022). 

  11. H. Jun, J. Cho, K. Lee, H.-Y. Son, K. Kim, H. Jin, and K.？Kim, "HBM (High Bandwidth Memory) DRAM Technology？and Architecture", 2017 IEEE International Memory Workshop？(IMW), Monterey, CA, USA, 16947916 (2017). 

  12. A. K. Singh, K. M. Sullivan, G. R. Leal, and T. Gong,？"Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules", International Symposium on？Microelectronics, 2019(1), 000001-000005 

  13. D. U. Lee, H. S. Cho, J. Kim, Y. J. Ku, S. Oh, C. D. Kim,？H. W. Kim, W. Y. Lee, T. K. Kim, T. S. Yun, M. J. Kim, S. Lim,？S. H. Lee, B. K. Yun, J. I. Moon, J. H. Park, S. Choi, Y. J. Park,？C. K. Lee, C. Jeong, J.-S. Lee, S. H. Lee, W. S. We, J. C. Yun,？D. Lee, J. Shin, S. Kim, J. Lee, J. Choi, Y. Ju, M.-J. Park,？K. S. Lee, Y. Hur, D. Shim, S. Lee, J. Chun, and K.-W. Jin,？"22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo？Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST", 2020 IEEE International Solid？State Circuits Conference (ISSCC), 334-336 (2020). 

  14. K. J. Han, "System Packaging Technology Development Trends",？KIEES Magazine: Electromagnetic Technology, 31(1), 31-40 (2020). 

  15. S. Y. Hou, W. C. Chen, C. Hu, C. Chiu, K. C. Ting, T. S. Lin,？W. H. Wei, W. C. Chiou, Vic J. C. Lin, Victor C. Y. Chang,？C. T. Wang, C. H. Wu, and D. Yu, "Wafer-Level Integration？of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology", IEEE Transactions on Electron？Devices, 64(10), 4071-4077 (2017). 

    상세보기

  16. R. Chaware, G. Hariharan, J. Lin, I. Singh, G. O'Rourke, K.？Ng, S. Y. Pai, Z. Huang, and S. K. Cheng, "Assembly Challenges？in Developing 3D IC package with Ultra High Yield？and High Reliability", 2015 IEEE 65th Electronic Components？and Technology Conference (ECTC), 1447-1451 (2015). 

  17. G. Duan, Y. Kanaoka, R. McRee, B. Nie, and R. Manepalli,？"Die Embedding Challenges for EMIB Advanced Packaging？Technology", 2021 IEEE 71st Electronic Components and？Technology Conference (ECTC), 1-7 (2021). 

  18. R. Mahajan, R. Sankman, N. Patel, D.-W. Kim, K. Aygun, Z.？Qian, Y. Mekonnen, I. Salama, S. Sharan, D. Iyengar, and D.？Mallik, "Embedded Multi-Die Interconnect Bridge (EMIB) - A High Density High Bandwidth Packaging Interconnect", 2016 IEEE 66th ECTC Conference, 557-565 (2016). 

  19. A. C. Durgun, Z. Qian, K. Aygun, R. Mahajan, T. T. Hoang,？and S. Y. Shumarayev, "Electrical Performance Limits of Fine？Pitch Interconnects for Heterogeneous Integration", 2019？IEEE 69th ECTC conference, 667-673 (2019). 

  20. R. Mahajan, Z. Qian, R. S. Viswanath, S. Srinivasan, K. Aygun,？W.-L. Jen, S. Sharan, and A. Dhall, "Embedded Multidie？Interconnect Bridge - A Localized, High-Density Multichip？Packaging Interconnect", IEEE Transactions on Components,？Packaging, and Manufacturing Technology, 9(10), 1952-1962 

    상세보기

  21. B. M. D. Sawyer, Y. Suzuki, R. Furuya, C. Nair, T.-C. Huang,？V. Smet, K. Panayappan, V. Sundaram, and R. Tummala,？"Design and Demonstration of a 2.5-D Glass Interposer BGA？Package for High Bandwidth and Low Cost", IEEE Transactions？on Components, Packaging and Manufacturing Technology, 7(4), 552-562 (2017). 

    상세보기

  22. K.-L. Suk, S. H. Lee, J. Y. Kim, S. W. Lee, H. J. Kim, S. C.？Lee, P. W. Kim, J. S. Byun, D.-W. Kim, and Dan Oh, "Low？Cost Si-Less RDL Interposer Package for High Performance？Computing Applications", 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 64-69 (2018). 

  23. J. Lee, and M. Kelly. "Amkor's 2.5 D Package and HDFO-Advanced？Heterogeneous Packaging Solutions", China Integrated Circuits (2018). 

  24. S. C. Hong, W. G. Lee, W. J. Kim, J. H. Kim, and J. P. Jung,？"Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking", Microelectronics Reliability, 51(12), 2228-2235 (2011) 

    상세보기

  25. D.-H. Jung, A. Sharma, K.-H. Kim, Y. C. Choo, and J. P. Jung,？"Effect of Current Density and Plating Time on Cu Electroplating？in TSV and Low Alpha Solder Bumping", Journal of？Materials Engineering and Performance, 24, 1107-1115 (2015). 

    상세보기

  26. H. C Kim, M. J. KIM, Y. Seo, Y. Lee, S. Choe, Y. G. Kim,？S. K. Cho, and J. J. Kim, "Bottom-Up Filling of TSV-Scaled？Trenches by Using Step Current Electrodeposition", ECS？Electrochemistry Letters, 4(10) (2015). 

    상세보기

  27. S. Thangaraju, L. England, M. Rabie, D. Zhang, G. Kumarapuram,？R. McGowan, A. Selsley, R. R. Giridharan, S. Gu, V.？Seshachalam, C. Wang, S. Kakita, S. Baral, W. Kim, and H.？Edmundson, "Successful void free gap fill of 3㎛, high AR？via middle, Through Silicon Vias at wafer level", 25th Annual？SEMI Advanced Semiconductor Manufacturing Conference？(ASMC 2014), 51-56 (2014). 

  28. S. Kim, S. Kim, K. Cho, T. Shin, H. Park, D. Lho, S. Park,？K. Son, G. Park, and J. Kim, "Processing-in-memory in High？Bandwidth Memory (PIM-HBM) Architecture with Energy-efficient？and Low Latency Channels for High Bandwidth System",？2019 IEEE 28th Conference on Electrical Performance？of Electronic Packaging and Systems (EPEPS), 1-3 (2019). 

  29. S. Kim, S. Kim, K. Cho, T. Shin, H. Park, D. Lho, S. Park,？K. Son, G. Park, S. Jeong, Y. Kim, and J. Kim, "Signal Integrity？and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory (PIM-HBM) Scheme",？IEEE Transactions on Components, Packaging and Manufacturing？Technology, 11(11), 1955-1970 (2021). 

    상세보기

  30. S. Kim, T. Shin, H. Park, D. Lho, K. Son, K. Kim, J. Park,？S. Choi, J. Kim, H. Kim, and J. Kim, "Signal Integrity Design？and Analysis of a Spiral Through-Silicon Via (TSV) Array？Channel for High Bandwidth Memory (HBM)", 2021 IEEE？Electrical Design of Advanced Packaging and Systems (EDAPS), 1-3 (2021). 

  31. G. B. Hamad, S. R. Hasan, O. A. Mohamed, and Y. Savaria,？"Characterizing, modeling, and analyzing soft error propagation？in asynchronous and synchronous digital circuits",？Microelectronics Reliability, 55(1), 238-250 (2015). 

    상세보기

  32. S. Kumar, S. Agarwal, and J. P. Jung. "Soft error issue and？importance of low alpha solders for microelectronics packaging",？Rev. Adv. Mater. Sci., 34, 185-202 (2013). 

    상세보기

  33. D. Jung, S. Agarwal, S. Kumar, and J. P. Jung, "High Shear？Speed Characteristics of Sub-100 ㎛ Low Alpha SAC105？Solder Bump Directly Fabricated on Cu Filled Through Si Via？for 3D Integration", Journal of Microelectronics and Electronic？Packaging, 12(3), 161-169 (2015). 

  34. J. H. Lau, "Recent Advances and Trends in Advanced Packaging",？IEEE Transactions on Components, Packaging and？Manufacturing Technology, 12(2), 228-252 (2022). 

    상세보기

  35. D. Stow, Y. Xie, T. Siddiqua, and G. H. Loh, "Cost-effective？design of scalable high-performance systems using active and？passive interposers", 2017 IEEE/ACM International Conference？on Computer-Aided Design (ICCAD), 1-8 (2017). 

  36. G. H. Loh, et al., "A Research Retrospective on AMD's Exascale？Computing Journey", ISCA '23: Proceedings of the 50th？Annual International Symposium on Computer Architecture, 81, 1-14 (2023). 

  37. R. Swaminathan, "Advanced packaging: Enabling Moore's？Law's next frontier through heterogeneous integration", IEEE？Hot Chip Conference, 1-25 (2021). 

  38. L. Ji, F. X. Che, H. M. Ji, H. Y. Li, and M. Kawano, "Wafer-to-Wafer Hybrid Bonding Development by Advanced Finite？Element Modeling for 3-D IC Packages", IEEE Transactions？on Components, Packaging and Manufacturing Technology, 10(12), 2106-2117 (2020). 

    상세보기

  39. M.-H. Roh, A. Sharma, J.-H. Lee, and J. P. Jung, "Extrusion？Suppression of TSV Filling Metal by Cu-W Electroplating for？Three-Dimensional Microelectronic Packaging", Metallurgical？and Materials Transactions A, 46, 2051-2062 (2015). 

  40. J. J. Ong, W. L. Chiu, O. H. Lee, C. W. Chiang, H. H. Chang,？C. H. Wang, K. C. Shie, S. C. Yang, D. P. Tran, K. N. Tu,？and C. Chen, "Low-Temperature Cu/SiO2 Hybrid Bonding？with Low Contact Resistance Using (111)-Oriented Cu Surfaces",？Materials, 15(5), 1888 (2022). 

    상세보기

  41. M.-F. Chen, F.-C. Chen, W.-C. Chiou, and D. C. H. Yu, "System？on Integrated Chips (SoIC(TM) for 3D Heterogeneous？Integration", 2019 IEEE 69th Electronic Components and？Technology Conference (ECTC), 594-599 (2019).？ 

  42. W.-L. Chiu, O.-H. Lee, C.-W. Chiang, and H.-H. Chang,？"Low-Temperature Wafer-to-Wafer Hybrid Bonding by？Nanocrystalline Copper", 2022 IEEE 72nd Electronic Components？and Technology Conference (ECTC), 679-684 (2022). 

  43. M. F. Chen, C. S. Lin, E. B. Liao, W. C. Chiou, C. C. Kuo,？C. C. Hu, C. H. Tsai, C. T. Wang, and D. Yu, "SoIC for Low-Temperature, Multi-Layer 3D Memory Integration", 2020？IEEE 70th Electronic Components and Technology Conference (ECTC), 855-860 (2020). 

  44. H. Seo, H. Park, and S. E. Kim, "Cu-SiO 2 Hybrid Bonding",？J. Microelectron. Packag. Soc., 27(1), 17-24 (2020). 

  45. T.-H. Hung, T.-C. Kang, S.-Y. Mao, T.-C. Chou, H.-W. Hu,？H.-Y. Chiu, C.-L. Shih, and K.-N. Chen, "Investigation of Wet？Pretreatment to Improve Cu-Cu Bonding for Hybrid Bonding？Applications", 2021 IEEE 71st Electronic Components and？Technology Conference (ECTC), 700-705 (2021). 

저자의 다른 논문 :

관련 콘텐츠

오픈액세스(OA) 유형

GOLD

오픈액세스 학술지에 출판된 논문

저작권 관리 안내
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로