다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기
Microelectronic engineering, v.86 no.10, 2009년, pp.2078 - 2085
Poljak, M. (Department of Electronics, Microelectronics, Computer and Intelligent Systems, Faculty of Electrical Engineering and Computing, University of Zagreb, Unska 3, HR-10000 Zagreb, Croatia) , Jovanovic, V. , Suligoj, T.
AI-Helper
The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have sho...
IEEE Transactions on Electron Devices Hisamoto 47 12 2320 2000 10.1109/16.887014
S.-K. Sung, S.-H. Lee, B.-Y. Choi, J.J. Lee, J.-D. Choe, E.S. Cho, et al., in: VLSI Technology Symposium 2006, Digest of Technical Papers, 2006, pp. 86-87.
Y. Bin, C. Leland, S. Ahmed, W. Haihong, S. Bell, Y. Chih-Yuh, et al., in: IEDM 2002, Digest of Technical Papers, 2002, pp. 251-254.
IEEE Transactions on Electron Devices Bansal 54 6 1409 2007 10.1109/TED.2007.895879
Solid-State Electronics Park 49 3 377 2005 10.1016/j.sse.2004.10.001
IEEE Electron Device Letters Hsu 28 5 443 2007 10.1109/LED.2007.895421
IEEE Electron Device Letters Lee 26 5 326 2005 10.1109/LED.2005.846587
10.1109/ISDRS.2007.4422327 M. Poljak, V. Jovanovi, T. Suligoj, Technological constraints of bulk FinFET structure in comparison with SOI FinFET. Proceeding of ISDRS 2007 International Semiconductor Device Research Symposium on CD: WP9-06-06.
International Technology Roadmap for Semiconductors (ITRS), 2007 Edition. <www.itrs.net>.
IEEE Transactions on Electron Devices Skotnicki 55 1 96 2008 10.1109/TED.2007.911338
Davinci User Guide W-2004.09, Synopsys Inc., 2004.
Cham 1986 Computer-aided Design and VLSI Device Development
IEEE Transactions on Electron Devices Esseni 50 3 802 2003 10.1109/TED.2002.807444
Microelectronics Journal Hu 37 613 2006 10.1016/j.mejo.2005.09.002
M. Poljak, P. Biljanovi, T. Suligoj, Comparison of 1D and 2D model of quantum effects in the simulation of sub-50nm double-gate MOSFETs. Proceedings of MIPRO International Convention MIPRO, 2007, pp. 78-83.
IEEE Transactions on Electron Devices Park 49 12 2222 2002 10.1109/TED.2002.805634
IEEE Transactions on Electron Devices Huang 48 880 2001 10.1109/16.918235
IEEE Transactions on Electron Devices Pei 49 8 1411 2002 10.1109/TED.2002.801263
IEEE Transactions on Electron Devices Suligoj 52 7 1392 2005 10.1109/TED.2005.850636
IEEE Transactions on Electron Devices Manoj 55 2 609 2008 10.1109/TED.2007.912996
Microelectronic Engineering Nawaz 85 1529 2008 10.1016/j.mee.2008.02.014
IEEE Transactions on Electron Devices Dollfus 51 5 749 2004 10.1109/TED.2004.826844
*원문 PDF 파일 및 링크정보가 존재하지 않을 경우 KISTI DDS 시스템에서 제공하는 원문복사서비스를 사용할 수 있습니다.
Copyright KISTI. All Rights Reserved.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.