초록 ▼

1. 고유전 박막의 증착 및 특성 분석
- BST MOCVD 공정 및 열처리 공정개발 : $Tox5.5{\AA}, {\epsilon}_r=250, J=1{\times}10^{-8}A/cm^2 at {\pm}1V$
- BSTON Sputter 공정 개발 : $Tox5.5{\AA}, {\epsilon}_r=400$
- ALD 공정을 이용한 STO 고유전 박막 개발 : uniformity<{\pm}8%$ at 4”, 유효두께 1.76nm, leakage current :

1. 고유전 박막의 증착 및 특성 분석
- BST MOCVD 공정 및 열처리 공정개발 : $Tox5.5{\AA}, {\epsilon}_r=250, J=1{\times}10^{-8}A/cm^2 at {\pm}1V$
- BSTON Sputter 공정 개발 : $Tox5.5{\AA}, {\epsilon}_r=400$
- ALD 공정을 이용한 STO 고유전 박막 개발 : uniformity<{\pm}8%$ at 4”, 유효두께 1.76nm, leakage current : $1O^{-7}A/cm^2 at 1V$
- Sol-gel 법을 이용하여 Pb계 완화형 강유전체 재료인 $Pb(Mg_{1/3}Nb_{2/3})O_3-PbTiO_3$[PMNT]박막을 형성함
- $800{\circ}C$에서 Pyrpchlore 상이 없는 순수한 Perovskite 상의 박막을 형성하여 2200${\AA}$의 두께에서 약 1650의 높은 유전상수 얻음
- $Hf(NO_3)_4 원료를 이용한 CVD 로 HfO_2$ 박막의 증착. native oxide가 존재할 때 열처리 후 $HfO_2$ 유전율이 20 이상으로 유지됨.
- $SiN/HfO_2/Al_2O_3/HfO_2와 같은 bi-layer를 이용하여 tox 12{\AA}$ 이하의 박막 증착.
- TBTDET 원료를 이용한 $Ta_2O_5 박막 증착, 380{\circ}C$ 저온에서 uniformity 5% 미만 확인
- 주성엔지니어링과의 공동 연구를 통해 $MIM Ta_2O_5에서 tox 21{\AA}$ 획득
- XRF, TEM, EDS, ellipsometer 등의 다양한 분석도구의 조합으로 극초박막에서의 조성과 두께변화를 분석
2. 금속 박막 증착 및 특성 분석
- Pt, Ru, $RuO_2$ 박막 MOCVD 공정 확립 : *step coverage = 90% at the contact hole of $0.25{\mu}m diameter, aspect ratio = 6 *uniformity={\pm}5%$
- Ru 박막 위에 $RuO_2$를 증착하고 이를 환원함으로써, mgged한 Ru 박막을 얻는데 성공
- $500{\AA}두께의 박막을 700{\circ}C$에서 열처리한 결과 박리되지 않음을 확인
3. 확산방지막 증착 기술연구
- $TiCl_4, AlCl_3$등의 Cl계 CVD 소스를 이용한 증착조건 확립 및 증착거동에 대한 연구수행.
- annealing 조건과 전극 물짐 변화에 따른 산화 mechanism의 변화 연구

Abstract ▼

The fabricating technology of capacitors for ULSI devices is essential to next-generation DRAM in which the capacitor is used for storing data. The technology includes the MOCVD or ALD deposition method of high-k thin films and electrodes, the MOCVD deposition method of a diffusion barrier for integ

The fabricating technology of capacitors for ULSI devices is essential to next-generation DRAM in which the capacitor is used for storing data. The technology includes the MOCVD or ALD deposition method of high-k thin films and electrodes, the MOCVD deposition method of a diffusion barrier for integrating processes, and various electrical and structural analysis methods for characterizing the fabricated capacitors. Because capacitors for a next-generation DRAM memory device of about 0.13$\mu$m or less must be fabricated by a series of CVD or ALD technologies, the first point of our researches is the realization of high-k materials and processes approximating tox=l $\AA$ on the basis of now immature (Ba,Sr) TiO$_3$ dielectric MOCVD technology, a MOCVD technology of metal thin films such as Pt, Ru, SrRuO$_3$ used for electrodes, and a CVD technology of diffusion barriers such as TiSiN, TiAIN for integrating processes. This is a semiconductor processing technology, which is necessary for one of our country's major industries. After the setup of this fundamental technology capacitor structures or materials under development by industries and further for 16, 64 giga DRAM are researched. This is our second point. By now when dielectrics are low-$\kappa$ materials such as SiO$_2$/SiN or TaO, the higher integration is realized by the technology of increasing the surface area in Si electrodes. It is supposed that although high-k materials such as BST are used for dielectrics, the same technology of increasing the surface area in metal electrodes be also necessary at the era of giga DRAM. The third target of our researches is a search for new materials of showing far higher dielectric constant than BST. Although the BST thin film has far higher dielectric constant than previous materials, the dielectric constant decreases as the thickness of the thin film decreases. On the other hand, recently, the research on the high-k gate oxide are extensively proceeding. Especially, application of binary oxide or silicate materials is the most important topic of the research on the high-$\kappa$ gate oxide. Therefore, our research team began to study on deposition of HfO$_2$ thin films by CVD or ALD process and the field of study on high-$\kappa$ materials was extened to MOSFETs from capacitors.
The final goal of the development is to establish the fabrication technology of the next-generation capacitor and MOSFETS. And its subordinate objects are the development of the ALD or CVD deposition technology in high-k dielectrics, ferroelectrics, metal electrodes and gate oxide, and the development of their unit process. Moreover, the establishment of electrical and structural analysis techniques about the fabricated devices is also in interest.

목차 Contents

• 제1장 연구개발과제의 개요...12
• 제2장 국내외 기술개발 현황...14
• 제3장 연구개발수행 내용 및 결과...16
• 제1절 BST 박막의 증착 및 특성분석...16
• 제2절 ALD 공정을 이용한 STO 고유전 박막 개발...35
• 제3절 Pb계 새로운 고유전 물질 탐색...46
• 제4절 MOCVD법에 의한 $Ta_2O_5$ 박막 형성 및 특성 평가...54
• 제5절 새로운 gate oxide용 고유전 물질 탐색연구...58
• 제6절 전기적, 화학적 구조적 분석 기술 구축...61
• 제7절 금속 전극 박막 증착 기술 연구...80
• 제8절 확산방지막 증착 기술 연구...92
• 제4장 목표달성도 및 관련분야에의 기여도...97
• 제5장 연구개발결과의 활영계획 및 활용가능성...99
• 제6장 연구개발과정에서 수집한 해외과학기술정보...101
• 제7장 참고문헌...103