[논문]Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

Cho, Seong-Jae; Sun, Min-Chul; Kim, Ga-Ram; Kamins, Theodore I.; Park, Byung-Gook; Harris, James S. Jr.

doi:10.5573/jsts.2011.11.3.182

[국내논문] Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology 원문보기

Journal of semiconductor technology and science, v.11 no.3, 2011년, pp.182 - 189

Cho, Seong-Jae (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) , Sun, Min-Chul (Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) , Kim, Ga-Ram (Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) , Kamins, Theodore I. (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) , Park, Byung-Gook (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) , Harris, James S. Jr. (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University)

Abstract ▼ AI-Helper

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

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제안 방법

5. Energy band diagram analyses for comparing a standby mode (left) and an operating mode (right) between a GaAs TFET and an I-HTFET.
In this work, a Type-I (straddling) heterojunction nanowire tunneling field-effect transistor (I-HTFET) with a channel length of 50 nm based on Ge-Al_xGa_1-xAsGe structure has been proposed and simulated for an optimized device design with Al composition as a design variable. The optimum value was found to be around x=0.
This scheme realizes a TFET device with an enhanced I_on and a suppressed off-state current (I_off). In this work, a comparative study on Type-I heterojunction TFET (IHTFET) with homojunction TFETs based on various materials and an optimum design for an I-HTFET of GeAl_xGa_1-xAs-Ge system were performed by 3D device simulation to meet the HP requirements predicted by the most recent technology roadmap [7, 8].

성능/효과

4. Consequently, the analysis results support that introducing a heterojunction formed by Ge and Al_xGa_1-xAs enables to expect improved I_on by higher BTBT probability due to a small E_G of the source-side Ge and high electron mobility of Al_xGa_1-xAs channel while keeping I_off sufficiently low by a large E_G of Al_xGa_1-xAs which reduces GIDL at the same time.
25. Judging from the results made so far on the fundamental direct current (DC) parameters, SS, V_th, I_on, and I_off, it is concluded that the optimum Al composition needs to be around 20%.

후속연구

For some devices, even a lower doping concentration in either source or drain junction demonstrates a better performance. For this reason, S/D doping concentrations were intentionally controlled for each device to demonstrate its highest I^on/I^off ratio with invariance in I^on by suppressing I^off effectively, by which more reliable and fair comparisons among the devices in their best states were made possible. In Fig.

참고문헌 (13)

W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less than 60 mV/dec," IEEE Electron Device Lett., Vol.28, No.8, Aug., 2007.

상세보기
P.-F. Guo, L.-T. Yang, Y. Yang, L. Fan, G.-Q. Han, G. S. Samudra, and Y.-C. Yeo, "Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current," IEEE Electron Device Lett., Vol.30, No.9, Sep., 2009.

상세보기
W. Y. Choi, "Comparative Study of Tunneling Field-Effect Transistors and Metal-Oxide- Semiconductor Field-Effect Transistors," Jpn. J. Appl. Phys., Vol.49, No.4, pp.04DJ12-1-04DJ12-3, Apr., 2010.

상세보기
E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, "Device Physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications," J. Appl. Phys., Vol.103, No.10, pp.104504-1-104504-5, May, 2008.

상세보기
J. Knoch and J. Appenzeller, "Modeling of High- Performance p-Type III-V Heterojunction Tunnel FETs," IEEE Electron Device Lett., Vol.31, No.4, Apr., 2010.

상세보기
K. Ganapathi and S. Salahuddin, "Heterojunctino Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High ON Current," IEEE Electron Device Lett., Vol.32, No.5, pp.689- 691, May, 2011.

상세보기
ATLAS User's Manual, Silvaco International, Santa Clara, CA, Nov/Dec., 2008.
Process Integration, Devices & Structures (PIDS), International Technology Roadmap for Semiconductors (ITRS), 2009 edition.
Y. Apanovich, P. Blakey, R. Cottle, E. Lyumkis, B. Polsky, A. Shur, and A. Tcherniaev, "Numerical simulation of submicrometer devices including coupled nonlocal transport and nonisothermal effects," IEEE Trans. Electron Devices, Vol.42, No.2, pp.890-898, May, 1995.

상세보기
O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of Tunneling Field-Effect Transistors Using Strained -Silicon/Strained-Germanium Type-II Staggered Heterojunctions," IEEE Electron Device Lett., Vol.29, No.9, pp.1074-1077, Sep., 2008.

상세보기
M.-H. Juang, P.-S. Hu, and S.-L. Jang, "Formation of lateral SiGe tunneling field-effect transistors on the SiGe/oxide/Si-substrate," Semicond. Sci. Technol., Vol.24, No.2, pp.025019-1-025019-4, Feb., 2009.

상세보기
G. B. Stringfellow, "Electron mobility in $Al_{x}Ga_{1}-_{x}As$ ," J. Appl. Phys., Vol.50, No.6, pp.4178-4183, Jun., 1979.

상세보기
A. K. Saxena, "Electron mobility in $Ga_{1-x}AL_{x}As$ alloys," Phys. Rev. B: Condens. Matter, Vol.24, No.6, pp.3295-3302, Sep., 1981.

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